Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > comp.parallel > #411

[ecsi-2] Call for Papers > ESLsyn-Electronic System Level Synthesis Conf. > May31-June1 > Co-located with DAC:

Cross-posted to 2 groups.

Show all headers | View raw

[http://www.ecsi.org//sites/default/files/images/ESLsyn%202013%20Mailing%20L
ogo_3.png]<http://www.ecsi.org/eslsyn>

Call for Contributions

ESLsyn
May 31 - June 1, 2013
Austin , TX, USA
Co-located with DAC!
General Chair:
Achim Rettberg,
University of Oldenburg, Germany
Program Co-Chairs:
Andreas Gerstlauer,
University of Texas, Austin
Marcio Kreutz,
Federal University of Rio Grande do Norte, Brazil
Organization Chair:
Adam Morawiec,
ECSI, France
Paper Submission Deadline: February 26, 2013
Submission Requirements:
Full papers (up to 6 pages, double-column IEEE format)
Submitted papers should be anonymous, original unpublished work and not be
under consideration for publication elsewhere.
The conference proceedings will be published in electronic form with an ISSN
and ISBN number and made available on the ECSI website and IEEE Xplore
(tbc).
Selected best papers from several ESLsyn conference editions will be
published in a book edited by SPRINGER.
Contacts:
eslsyn2013@ecsi.org<mailto:eslsyn2013@ecsi.org>
www.ecsi.org/eslsyn<http://www.ecsi.org/eslsyn>


The Electronic System Level Synthesis Conference - ESLsyn provides an
international forum for discussion of topics related to automated
system-level design, including but not limited to efficient modelling,
synthesis, exploration and verification of systems all the way from
high-level specifications down to embedded hardware and software
implementations.

Contributors are invited to submit papers on topics related to the design
and verification of complex, programmable electronic products:

 *
The development of product architectures and specifications, including the
incorporation and configuration of IP
 *
The mapping of applications onto a product platform, including
hardware/software partitioning and processor optimization
 *
The creation of pre-silicon, virtual hardware platforms for software
development
 *
The automated synthesis of hardware and software implementations for a given
architecture
 *
The development of formal methods for verifying hardware and software
Other ESLsyn topics may include:

 *
Cyber-Physical Systems/Platforms related to ESL design flows
 *
High-Level/Behavioral/Architectural Synthesis of hardware designs in
cooperation with ESL design flows
 *
Embedded software synthesis that is used as part of ESL design flows
The above list is not an exhaustive list of topics addressed by ESLsyn;
contributions related to ESLsyn problems in general not listed here are
highly welcome. Submissions may be theoretical scientific papers, research
in progress, case studies, tool use cases and best practice, as well as
industry experiences.
ESLsyn is organized with the technical co-sponsorship of CEDA.
[http://www.ecsi.org//sites/default/files/images/CEDA_Logo_small2.jpg]


Please click here if you wish to be removed from this mailing
list.<http://www.ecsi.org/remove-mailing-list>
Please do not respond to this email address. Direct contact information can
be found at www.ecsi.org<http://www.ecsi.org>.





------ End of Forwarded Message

Back to comp.parallel | Previous | Next | Find similar | Unroll thread

Thread

[ecsi-2] Call for Papers > ESLsyn-Electronic System Level Synthesis Conf. > May31-June1 > Co-located with DAC: "info@ecsi.org" <info@ecsi.org> - 2013-01-05 17:17 +0000

csiph-web