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Groups > comp.os.linux.misc > #88473 > unrolled thread
| Started by | c186282 <c186282@nnada.net> |
|---|---|
| First post | 2026-06-28 00:36 -0400 |
| Last post | 2026-07-07 07:51 -0700 |
| Articles | 9 on this page of 89 — 11 participants |
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IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-06-28 00:36 -0400
[HK01]IBM研發首款0.7nm晶片 指甲大小塞滿1000億電晶體 效能飆升50% "Mr. Man-wai Chang" <toylet.toylet@gmail.com> - 2026-06-29 00:01 +0800
Re: IBM - New SUB-Nanometer STACKED Chip Charlie Gibbs <cgibbs@kltpzyxm.invalid> - 2026-06-28 18:09 +0000
Re: IBM - New SUB-Nanometer STACKED Chip "Mr. Man-wai Chang" <toylet.toylet@gmail.com> - 2026-06-29 13:11 +0800
Re: IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-06-29 01:39 -0400
Re: IBM - New SUB-Nanometer STACKED Chip "Mr. Man-wai Chang" <toylet.toylet@gmail.com> - 2026-06-29 19:20 +0800
Re: IBM - New SUB-Nanometer STACKED Chip The Natural Philosopher <tnp@invalid.invalid> - 2026-06-29 12:57 +0100
Re: IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-06-30 05:14 -0400
Re: IBM - New SUB-Nanometer STACKED Chip "Mr. Man-wai Chang" <toylet.toylet@gmail.com> - 2026-06-30 21:51 +0800
Re: IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-06-30 12:06 -0400
Re: IBM - New SUB-Nanometer STACKED Chip Charlie Gibbs <cgibbs@kltpzyxm.invalid> - 2026-06-30 18:51 +0000
Re: IBM - New SUB-Nanometer STACKED Chip Paul <nospam@needed.invalid> - 2026-06-30 17:58 -0400
Re: IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-07-01 01:15 -0400
Re: IBM - New SUB-Nanometer STACKED Chip The Natural Philosopher <tnp@invalid.invalid> - 2026-07-01 10:15 +0100
Re: IBM - New SUB-Nanometer STACKED Chip rbowman <bowman@montana.com> - 2026-06-30 23:51 +0000
Re: IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-07-01 03:16 -0400
Re: IBM - New SUB-Nanometer STACKED Chip The Natural Philosopher <tnp@invalid.invalid> - 2026-07-01 10:05 +0100
Re: IBM - New SUB-Nanometer STACKED Chip rbowman <bowman@montana.com> - 2026-07-01 17:43 +0000
Re: IBM - New SUB-Nanometer STACKED Chip The Natural Philosopher <tnp@invalid.invalid> - 2026-07-01 20:23 +0100
Re: IBM - New SUB-Nanometer STACKED Chip rbowman <bowman@montana.com> - 2026-07-02 01:57 +0000
Re: IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-07-02 16:48 -0400
Re: IBM - New SUB-Nanometer STACKED Chip rbowman <bowman@montana.com> - 2026-07-02 21:32 +0000
Re: IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-07-02 18:15 -0400
Re: IBM - New SUB-Nanometer STACKED Chip The Natural Philosopher <tnp@invalid.invalid> - 2026-07-03 11:03 +0100
Re: IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-07-04 09:32 -0400
Re: IBM - New SUB-Nanometer STACKED Chip Charlie Gibbs <cgibbs@kltpzyxm.invalid> - 2026-07-04 17:06 +0000
Re: IBM - New SUB-Nanometer STACKED Chip "Carlos E. R." <robin_listas@es.invalid> - 2026-07-04 19:24 +0200
Re: IBM - New SUB-Nanometer STACKED Chip rbowman <bowman@montana.com> - 2026-07-04 18:20 +0000
Re: IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-07-04 23:37 -0400
Re: IBM - New SUB-Nanometer STACKED Chip The Natural Philosopher <tnp@invalid.invalid> - 2026-07-04 19:20 +0100
Re: IBM - New SUB-Nanometer STACKED Chip Rich <rich@example.invalid> - 2026-07-04 20:28 +0000
Re: IBM - New SUB-Nanometer STACKED Chip rbowman <bowman@montana.com> - 2026-07-04 20:47 +0000
Re: IBM - New SUB-Nanometer STACKED Chip Nuno Silva <nunojsilva@invalid.invalid> - 2026-07-05 00:33 +0100
Re: IBM - New SUB-Nanometer STACKED Chip rbowman <bowman@montana.com> - 2026-07-04 20:42 +0000
Re: IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-07-04 23:51 -0400
Re: IBM - New SUB-Nanometer STACKED Chip rbowman <bowman@montana.com> - 2026-07-05 06:57 +0000
Re: IBM - New SUB-Nanometer STACKED Chip "Carlos E. R." <robin_listas@es.invalid> - 2026-07-05 13:38 +0200
Re: IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-07-04 23:45 -0400
Re: IBM - New SUB-Nanometer STACKED Chip The Natural Philosopher <tnp@invalid.invalid> - 2026-07-05 10:49 +0100
Re: IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-07-06 00:33 -0400
Re: IBM - New SUB-Nanometer STACKED Chip "Carlos E. R." <robin_listas@es.invalid> - 2026-07-06 13:19 +0200
Re: IBM - New SUB-Nanometer STACKED Chip The Natural Philosopher <tnp@invalid.invalid> - 2026-07-06 12:39 +0100
Re: IBM - New SUB-Nanometer STACKED Chip Lawrence D’Oliveiro <ldo@nz.invalid> - 2026-07-08 07:49 +0000
Re: IBM - New SUB-Nanometer STACKED Chip "Carlos E. R." <robin_listas@es.invalid> - 2026-07-08 12:04 +0200
Re: IBM - New SUB-Nanometer STACKED Chip The Natural Philosopher <tnp@invalid.invalid> - 2026-07-08 11:10 +0100
Re: IBM - New SUB-Nanometer STACKED Chip rbowman <bowman@montana.com> - 2026-07-08 17:43 +0000
Re: IBM - New SUB-Nanometer STACKED Chip The Natural Philosopher <tnp@invalid.invalid> - 2026-07-08 19:02 +0100
Re: IBM - New SUB-Nanometer STACKED Chip "Carlos E. R." <robin_listas@es.invalid> - 2026-07-08 20:37 +0200
Re: IBM - New SUB-Nanometer STACKED Chip rbowman <bowman@montana.com> - 2026-07-08 17:41 +0000
Re: IBM - New SUB-Nanometer STACKED Chip Charlie Gibbs <cgibbs@kltpzyxm.invalid> - 2026-07-08 17:53 +0000
Re: IBM - New SUB-Nanometer STACKED Chip The Natural Philosopher <tnp@invalid.invalid> - 2026-07-08 19:02 +0100
Re: IBM - New SUB-Nanometer STACKED Chip "Carlos E. R." <robin_listas@es.invalid> - 2026-07-08 20:41 +0200
Re: IBM - New SUB-Nanometer STACKED Chip The Natural Philosopher <tnp@invalid.invalid> - 2026-07-06 12:32 +0100
Re: IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-07-01 00:48 -0400
Re: IBM - New SUB-Nanometer STACKED Chip rbowman <bowman@montana.com> - 2026-06-30 23:45 +0000
Re: IBM - New SUB-Nanometer.... physics? "quantum"? "Mr. Man-wai Chang" <toylet.toylet@gmail.com> - 2026-07-01 12:24 +0800
Re: IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-07-01 03:13 -0400
Re: IBM - New SUB .... quantum mechanics is quantitative philiosphy? "Mr. Man-wai Chang" <toylet.toylet@gmail.com> - 2026-07-01 15:29 +0800
Re: IBM - New SUB .... quantum mechanics is quantitative philiosphy? c186282 <c186282@nnada.net> - 2026-07-01 04:22 -0400
Re: IBM - New SUB .... quantum mechanics is quantitative philiosphy? "Mr. Man-wai Chang" <toylet.toylet@gmail.com> - 2026-07-01 23:41 +0800
Re: IBM - New SUB .... quantum mechanics is quantitative philiosphy? c186282 <c186282@nnada.net> - 2026-07-02 01:56 -0400
Re: IBM - New SUB .... quantum mechanics is FLAT? "Mr. Man-wai Chang" <toylet.toylet@gmail.com> - 2026-07-02 14:04 +0800
Re: IBM - New SUB .... quantum mechanics is FLAT? c186282 <c186282@nnada.net> - 2026-07-02 16:50 -0400
Re: IBM - New SUB .... quantum mechanics is FLAT? rbowman <bowman@montana.com> - 2026-07-02 21:26 +0000
Re: IBM - New SUB .... quantum mechanics is FLAT? c186282 <c186282@nnada.net> - 2026-07-02 18:11 -0400
Re: IBM - New SUB-Nanometer STACKED Chip Paul <nospam@needed.invalid> - 2026-06-30 22:09 -0400
Re: IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-07-01 03:29 -0400
Re: IBM - New SUB-Nanometer STACKED Chip The Natural Philosopher <tnp@invalid.invalid> - 2026-07-01 10:11 +0100
Re: IBM - New SUB-Nanometer STACKED Chip The Natural Philosopher <tnp@invalid.invalid> - 2026-07-01 10:08 +0100
Re: IBM - New SUB-Nanometer STACKED Chip Lawrence D’Oliveiro <ldo@nz.invalid> - 2026-07-08 07:46 +0000
Re: IBM - New SUB-Nanometer STACKED Chip "Carlos E. R." <robin_listas@es.invalid> - 2026-07-08 12:05 +0200
Re: IBM - New SUB-Nanometer STACKED Chip The Natural Philosopher <tnp@invalid.invalid> - 2026-07-08 11:13 +0100
Re: IBM - New SUB-Nanometer STACKED Chip The Natural Philosopher <tnp@invalid.invalid> - 2026-06-30 16:27 +0100
Re: IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-06-30 12:18 -0400
Re: IBM - New SUB-Nanometer STACKED Chip The Natural Philosopher <tnp@invalid.invalid> - 2026-06-30 17:32 +0100
Re: IBM - New SUB-Nanometer STACKED Chip rbowman <bowman@montana.com> - 2026-06-30 23:40 +0000
Re: IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-07-01 02:53 -0400
Re: IBM - New SUB-Nanometer STACKED Chip The Natural Philosopher <tnp@invalid.invalid> - 2026-07-01 10:01 +0100
Re: IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-07-01 00:17 -0400
Re: IBM - New SUB-Nanometer STACKED Chip rbowman <bowman@montana.com> - 2026-06-30 23:37 +0000
Re: IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-07-01 02:33 -0400
Re: IBM - New SUB-Nanometer STACKED Chip rbowman <bowman@montana.com> - 2026-06-30 23:28 +0000
Re: IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-07-01 02:04 -0400
Re: IBM - New SUB-Nanometer STACKED Chip Paul <nospam@needed.invalid> - 2026-07-01 04:33 -0400
Re: IBM - New SUB-Nanometer STACKED Chip c186282 <c186282@nnada.net> - 2026-06-29 01:34 -0400
Re: IBM - New SUB-Nanometer STACKED Chip Lawrence D’Oliveiro <ldo@nz.invalid> - 2026-07-07 01:21 +0000
Re: IBM - New SUB-Nanometer STACKED Chip rbowman <bowman@montana.com> - 2026-07-07 04:14 +0000
Re: IBM - New SUB-Nanometer STACKED Chip "Carlos E. R." <robin_listas@es.invalid> - 2026-07-07 08:31 +0200
Re: IBM - New SUB-Nanometer STACKED Chip John Ames <commodorejohn@gmail.com> - 2026-07-07 07:51 -0700
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| From | c186282 <c186282@nnada.net> |
|---|---|
| Date | 2026-07-01 02:33 -0400 |
| Message-ID | <RdadnTl6Wu0qKdn3nZ2dnZfqnPednZ2d@giganews.com> |
| In reply to | #88549 |
On 6/30/26 19:37, rbowman wrote: > On Tue, 30 Jun 2026 12:18:47 -0400, c186282 wrote: > >> IBM may have just built the Final Chip, so to speak. Better stuff >> will have to use very different technologies. > > IBM hasn't really built anything in a while. > > https://en.wikipedia.org/wiki/IBM_Microelectronics They're BEHIND it ... same thing, same $$$ > A friend spent his entire career at Essex Junction and timed his > retirement just right. He had interned at Fishkill when we were in > college, got his PhD, and segued into a full time IBM employee. That's > relatively unique in the tech industry. "Dilbert" was based on IBM corporate culture/thinking. Yes, sometimes absurd/insane ... but it HAS worked long term. Maybe sometimes you NEED some insanity. Not selling my stock. > Interestingly the last time I visited him before I moved out of the area > he had bought a PCjr and wasn't quite sure what to do with it. PC-Jr wasn't a great computer - but would still get most everything you needed DONE. More or less affordable too. IBM was never really geared for Joe Consumer - for 'biz' and above levels instead. They could not compete with Compaq and friends and still make a buck, so they just dumped that. Their old ThinkPads were pretty good, but once they outsourced them, well, NOT so great. For USERS, more than x-amount of home computer power is usually just WASTED - advertising hype. I do have one fairly strong desktop box - set it up (Linux) and parked it in the junk room, never used since. My cheapo laptops and mini-boxes are powerful enough for anything *I* need now. Had to re-install my MX security/streaming box. The last install (MX) didn't go quite right and the main desktop would HINT, but never actually GET there. Burned a lot of CPU doing "nothing" too - box got very hot. DID save most of the valuable apps/configs though so it was fairly easy this time after re-install. Good install now, and have CHEATED - used the MX "snapshot" utility to create a custom ISO with all my goodies on it. IF it craps again I can go right back to a fully working install. Taped the thumb drive TO the unit so it won't get lost.
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| From | rbowman <bowman@montana.com> |
|---|---|
| Date | 2026-06-30 23:28 +0000 |
| Message-ID | <naj1o0FgbvpU1@mid.individual.net> |
| In reply to | #88536 |
On Tue, 30 Jun 2026 16:27:24 +0100, The Natural Philosopher wrote: > "Transistor nodes have shrunk dramatically, with leading developers like > IBM advancing into the sub-1 nanometre realm (e.g., 0.7-nanometer tech). > However, absolute limits are rapidly approaching due to several factors: iirc terms like '5 nm process' no longer refer to any physical dimension so I'm curious what the actual gate size is on 0.7 nm tech. IBM sold their fab lines to GlobalFoundries and their '7 nm' tech was closer to Intel's 10 nm.
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| From | c186282 <c186282@nnada.net> |
|---|---|
| Date | 2026-07-01 02:04 -0400 |
| Message-ID | <RdadnT56Wu1HMNn3nZ2dnZfqnPednZ2d@giganews.com> |
| In reply to | #88548 |
On 6/30/26 19:28, rbowman wrote: > On Tue, 30 Jun 2026 16:27:24 +0100, The Natural Philosopher wrote: > >> "Transistor nodes have shrunk dramatically, with leading developers like >> IBM advancing into the sub-1 nanometre realm (e.g., 0.7-nanometer tech). >> However, absolute limits are rapidly approaching due to several factors: > > iirc terms like '5 nm process' no longer refer to any physical dimension > so I'm curious what the actual gate size is on 0.7 nm tech. > > IBM sold their fab lines to GlobalFoundries and their '7 nm' tech was > closer to Intel's 10 nm. Well, SEEMS like they've done the 1, or <1, nm stacked chip. They'll license that. Old company, but still kinda out-front in their tech AND biz sense. NOT gonna dump my stock. Alas, as mentioned here, this IS about as far as conventional electronics can go. Under 1nm the quantum issues fuck up everything. SO - we need entirely new tech paradigms now. For 'electronics' we HAVE crashed into Dr. Moore. Meanwhile, the stacked chips DO allow us to do more, if not faster, in the same chip profiles. There's money in that - for now. Five years ... as said, we need Something Completely Different. Maybe I'll be dead by then and won't care, maybe not, but "transistors" aren't gonna go any faster even as "AI" and a lot more DEMAND that. Still wonder if "deca-state" logic, where the intermediate values are stable and DON'T eat up power, can be done. Some 'latching', 'layered', design maybe. A few more layers per transistor. I have this vague vision in my head ... quantified analog, so to speak. One transistor, 2^10th possible values.
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| From | Paul <nospam@needed.invalid> |
|---|---|
| Date | 2026-07-01 04:33 -0400 |
| Message-ID | <1122jcb$1ns5s$1@dont-email.me> |
| In reply to | #88562 |
On Wed, 7/1/2026 2:04 AM, c186282 wrote:
> On 6/30/26 19:28, rbowman wrote:
>> On Tue, 30 Jun 2026 16:27:24 +0100, The Natural Philosopher wrote:
>>
>>> "Transistor nodes have shrunk dramatically, with leading developers like
>>> IBM advancing into the sub-1 nanometre realm (e.g., 0.7-nanometer tech).
>>> However, absolute limits are rapidly approaching due to several factors:
>>
>> iirc terms like '5 nm process' no longer refer to any physical dimension
>> so I'm curious what the actual gate size is on 0.7 nm tech.
>>
>> IBM sold their fab lines to GlobalFoundries and their '7 nm' tech was
>> closer to Intel's 10 nm.
>
> Well, SEEMS like they've done the 1, or <1, nm
> stacked chip.
You will need to see the dimensions of the whole thing,
to see which "chance" dimension is 1nm.
https://newsroom.ibm.com/2026-06-25-ibm-debuts-worlds-first-sub-1-nanometer-chip-technology
https://filecache.mediaroom.com/mr5mr_ibmnewsroom/201436/IBM-Research_TEM_4.jpg
The diagram here, is too hard to read. The FINFET is on the left. The Gate All Around
device in the center. The stacked P channel and N channel on the right.
https://www.eetimes.com/ibm-shows-sub-1-nm-chips-targeting-production-in-5-years/
They talk here, of two wafers being bonded vertically. Which might
be how the scheme maintains a semblance of manufacturability. Imagine
an 18" (450mm" wafer, aligned at the atomic level.
https://www.servethehome.com/ibm-outlines-sub-1nm-nanostack-transistor-technology/
Paul
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| From | c186282 <c186282@nnada.net> |
|---|---|
| Date | 2026-06-29 01:34 -0400 |
| Message-ID | <VaKcnSZYBtQtnt_3nZ2dnZfqnPudnZ2d@giganews.com> |
| In reply to | #88494 |
On 6/28/26 14:09, Charlie Gibbs wrote: > On 2026-06-28, c186282 <c186282@nnada.net> wrote: > >> https://www.techspot.com/news/112907-ibm-unveils-sub-1-nanometer-chip-architecture-stacks.html >> >> IBM unveils sub-1-nanometer chip architecture that stacks 100 >> billion transistors onto a fingernail-sized processor >> >> . . . >> >> Pretty impressive ... and stacking two (three?) layers >> really packs a lot in. >> >> NOT sure how they deal with the HEAT in the stacked >> design. >> >> 100 billion ... how many in the i4004 ? > > Dunno - but I do remember that manufacturers hit a wall for > a while when trying to get below 1 micrometer. It took some > time before memory chips larger than 64K became available. Found it in WikiPedia ... 2300 transistors ! And yea, I remember how long it took them to significantly shrink things. "Stacked" chips have long been of interest to save real estate and signal path, but again not revealed how IBM has managed to cope with the heat dissipation issues. The sub-nanometer bit ... that IS a significant step. BUT, the smaller you make things, the more likely natural radiation and even quantum effects will sneakily change bits. We've pushed Moore further than I thought he could be, but ...
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| From | Lawrence D’Oliveiro <ldo@nz.invalid> |
|---|---|
| Date | 2026-07-07 01:21 +0000 |
| Message-ID | <112hkad$2h4su$2@dont-email.me> |
| In reply to | #88494 |
On Sun, 28 Jun 2026 18:09:44 GMT, Charlie Gibbs wrote: > Dunno - but I do remember that manufacturers hit a wall for a while > when trying to get below 1 micrometer. Part of the way past the barrier was, shall we say, redefining the problem. Down to, I’m not sure, maybe 100nm or a bit below, that measurement was the actual feature size. Nowadays, what the companies call a “1nm” process is still working with transistors with dimensions more like 30nm; they are just stacking them in layers to get an equivalent density to 1nm if you were working only in two dimensions.
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| From | rbowman <bowman@montana.com> |
|---|---|
| Date | 2026-07-07 04:14 +0000 |
| Message-ID | <nb3cpuF4kctU2@mid.individual.net> |
| In reply to | #88741 |
On Tue, 7 Jul 2026 01:21:18 -0000 (UTC), Lawrence D’Oliveiro wrote: > On Sun, 28 Jun 2026 18:09:44 GMT, Charlie Gibbs wrote: > >> Dunno - but I do remember that manufacturers hit a wall for a while >> when trying to get below 1 micrometer. > > Part of the way past the barrier was, shall we say, redefining the > problem. Photolithography was one limit. State of the art now is extreme untraviolet lithography with a 13.5 nm wavelength. ASML in the Netherlands is the sole source although you can bet the Chinese are working overtime. Next stop is x-rays. It has been done on an experimental basis but is even more costly.
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| From | "Carlos E. R." <robin_listas@es.invalid> |
|---|---|
| Date | 2026-07-07 08:31 +0200 |
| Message-ID | <nb3kpmF5u6cU1@mid.individual.net> |
| In reply to | #88741 |
On 2026-07-07 03:21, Lawrence D’Oliveiro wrote:
> On Sun, 28 Jun 2026 18:09:44 GMT, Charlie Gibbs wrote:
>
>> Dunno - but I do remember that manufacturers hit a wall for a while
>> when trying to get below 1 micrometer.
>
> Part of the way past the barrier was, shall we say, redefining the
> problem.
>
> Down to, I’m not sure, maybe 100nm or a bit below, that measurement
> was the actual feature size.
>
> Nowadays, what the companies call a “1nm” process is still working
> with transistors with dimensions more like 30nm; they are just
> stacking them in layers to get an equivalent density to 1nm if you
> were working only in two dimensions.
But but but... but that is cheating!
--
Cheers,
Carlos E.R.
ES🇪🇸, EU🇪🇺;
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| From | John Ames <commodorejohn@gmail.com> |
|---|---|
| Date | 2026-07-07 07:51 -0700 |
| Message-ID | <20260707075156.00001d6e@gmail.com> |
| In reply to | #88745 |
On Tue, 7 Jul 2026 08:31:18 +0200 "Carlos E. R." <robin_listas@es.invalid> wrote: > > Part of the way past the barrier was, shall we say, redefining the > > problem. > > But but but... but that is cheating! That's Marketing, my friend!
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