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Creating a "European CMOS 2.0 Army"

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  Creating a "European CMOS 2.0 Army" Mild Shock <janburse@fastmail.fm> - 2026-07-13 07:25 +0200
    Micro penis walking around with a rucksack (Was: Creating a "European CMOS 2.0 Army") Mild Shock <janburse@fastmail.fm> - 2026-07-13 07:27 +0200
      Light Tuning of LLMs Locally (Was: Micro penis walking around with a rucksack) Mild Shock <janburse@fastmail.fm> - 2026-07-13 13:27 +0200
      Light Tuning of LLMs Locally (Was: Micro penis walking around with a rucksack) Mild Shock <janburse@fastmail.fm> - 2026-07-13 13:28 +0200
        PCIe 6.0 x16 versus LPDDR5X-8000 latency (Re: Light Tuning of LLMs Locally) Mild Shock <janburse@fastmail.fm> - 2026-07-13 15:56 +0200
    TSMC's 2nm (N2) node and the 7 GHz target (Re: Creating a "European CMOS 2.0 Army") Mild Shock <janburse@fastmail.fm> - 2026-07-14 14:12 +0200
      pi-WAM is just like Laika3, the first Dog on Mars (Was: TSMC's 2nm (N2) node and the 7 GHz target) Mild Shock <janburse@fastmail.fm> - 2026-07-15 18:10 +0200
        So memory bandwidth is no issue at all (Re: pi-WAM is just like Laika3, the first Dog on Mars) Mild Shock <janburse@fastmail.fm> - 2026-07-15 18:37 +0200
          For iGPU which acts as a APU RAM is shared (Re: So memory bandwidth is no issue at all) Mild Shock <janburse@fastmail.fm> - 2026-07-16 17:09 +0200
            Village Idiot wants 8088 back [Puting Troll] (Re: For iGPU which acts as a APU RAM is shared) Mild Shock <janburse@fastmail.fm> - 2026-07-16 23:03 +0200
              VT100 25 x 80 terminal = 2000 Bytes (Re: Village Idiot wants 8088 back [Puting Troll]) Mild Shock <janburse@fastmail.fm> - 2026-07-16 23:09 +0200
        From short-cut parallelism to true parallelism [π-WAM Musings] (Re: pi-WAM is just like Laika3, the first Dog on Mars) Mild Shock <janburse@fastmail.fm> - 2026-08-27 17:58 +0200
          I think Erlang is completely dead. And I repeat it. (Was: From short-cut parallelism to true parallelism [π-WAM Musings]) Mild Shock <janburse@fastmail.fm> - 2026-08-29 03:05 +0200

#15628 — Creating a "European CMOS 2.0 Army"

Hi,

For marketing purposes people
typically look at the race towards
2nm, and we find:

A month ago, Apple lost its exclusivity
on 3 nm smartphone processors with
MediaTek’s Dimensity 9400 chip, integrated
in the Vivo X200 Pro smartphone. Qualcomm
is also in the race with its recently
unveiled Snapdragon 8 Elite and set to
power the Xiaomi 15 Pro in 2025. However,
Apple should regain its position as innovation
leader in 2026 with the release of the
iPhone 18, which should feature the A20
chip built on TSMC’s 2 nm process."

But there is a vertical vias revolution
going on as well, some SOCs typically
being at 18 layers now:

Zooming Into a CPU (It's Incredible)
https://www.youtube.com/watch?v=Bez-2cvYja0

imec has coined the term CMOS 2.0:

LEUVEN (Belgium), MARCH 12th, 2026 — Imec,
a world-leading research and innovation hub
in advanced semiconductor technologies, has
launched a first-of-its-kind consortium with
26 European university groups that will jointly
work on the technology roadmap beyond
CMOS scaling (CMOS 2.0).
https://www.imec-int.com/en/press/imec-launches-university-consortium-around-next-generation-chips

So we might see more mobile grade GPUs.

Bye

[toc] | [next] | [standalone]

#15629 — Micro penis walking around with a rucksack (Was: Creating a "European CMOS 2.0 Army")

Hi,

So we might see more mobile grade GPUs,
on a finger nail, without any cooling fans
in the future? Yes my Redmi smart phone doesn't

have any cooling fans, I do not intend to put
a RTX 5090 in a rucksack and carry a 600 W battery
pack (*), to have some AI on my phone.

Have Fun!

Bye

(*) The Bluetti Premium 30 V2 is 4.3 Kg heavy:
https://www.galaxus.ch/de/s4/product/bluetti-premium-30-v2-320-wh-430-kg-power-station-65489839

Mirco penis was loosing his marbles:
> you stinking sack of rocks, you can't read your 
> own redundant links. Watch the prices for the
 > Ryzen AI laptops. Fucking idiot. Not worth the
 > price for what they give in AI. Those are embedded
 > cpu/gpu cretin, you don't need to read more.

Mild Shock schrieb:
> Hi,
> 
> For marketing purposes people
> typically look at the race towards
> 2nm, and we find:
> 
> A month ago, Apple lost its exclusivity
> on 3 nm smartphone processors with
> MediaTek’s Dimensity 9400 chip, integrated
> in the Vivo X200 Pro smartphone. Qualcomm
> is also in the race with its recently
> unveiled Snapdragon 8 Elite and set to
> power the Xiaomi 15 Pro in 2025. However,
> Apple should regain its position as innovation
> leader in 2026 with the release of the
> iPhone 18, which should feature the A20
> chip built on TSMC’s 2 nm process."
> 
> But there is a vertical vias revolution
> going on as well, some SOCs typically
> being at 18 layers now:
> 
> Zooming Into a CPU (It's Incredible)
> https://www.youtube.com/watch?v=Bez-2cvYja0
> 
> imec has coined the term CMOS 2.0:
> 
> LEUVEN (Belgium), MARCH 12th, 2026 — Imec,
> a world-leading research and innovation hub
> in advanced semiconductor technologies, has
> launched a first-of-its-kind consortium with
> 26 European university groups that will jointly
> work on the technology roadmap beyond
> CMOS scaling (CMOS 2.0).
> https://www.imec-int.com/en/press/imec-launches-university-consortium-around-next-generation-chips 
> 
> 
> So we might see more mobile grade GPUs.
> 
> Bye

[toc] | [prev] | [next] | [standalone]

#15631 — Light Tuning of LLMs Locally (Was: Micro penis walking around with a rucksack)

Hi,

Interestingly  "Strix" (Strix Point) is no longer
the top news, as "Krackan" (Krackan Point) and the
massive "Halo" (Strix Halo) have officially stepped
into the spotlight.

My tester Acer Swift Go was already "Krackan" (Krackan
Point. So a shift from local inferencing, to limited
local machine learning is possible. And AMD
Ryzen is hitting the drums:

AMD Ryzen™ AI Halo: Build the AI You Want. Your Stack. Your Rules.
https://www.youtube.com/watch?v=lxTaJ5LDY20

Pre-orders for the platform open in June, featuring
128GB of unified memory which enables developers to
run intensive workloads with models up to 200
billion parameters.

LoL

Have Fun!

Bye

Mild Shock schrieb:
> Hi,
> 
> So we might see more mobile grade GPUs,
> on a finger nail, without any cooling fans
> in the future? Yes my Redmi smart phone doesn't
> 
> have any cooling fans, I do not intend to put
> a RTX 5090 in a rucksack and carry a 600 W battery
> pack (*), to have some AI on my phone.
> 
> Have Fun!
> 
> Bye
> 
> (*) The Bluetti Premium 30 V2 is 4.3 Kg heavy:
> https://www.galaxus.ch/de/s4/product/bluetti-premium-30-v2-320-wh-430-kg-power-station-65489839 
> 
> 
> Mirco penis was loosing his marbles:
>> you stinking sack of rocks, you can't read your own redundant links. 
>> Watch the prices for the
>  > Ryzen AI laptops. Fucking idiot. Not worth the
>  > price for what they give in AI. Those are embedded
>  > cpu/gpu cretin, you don't need to read more.
> 
> Mild Shock schrieb:
>> Hi,
>>
>> For marketing purposes people
>> typically look at the race towards
>> 2nm, and we find:
>>
>> A month ago, Apple lost its exclusivity
>> on 3 nm smartphone processors with
>> MediaTek’s Dimensity 9400 chip, integrated
>> in the Vivo X200 Pro smartphone. Qualcomm
>> is also in the race with its recently
>> unveiled Snapdragon 8 Elite and set to
>> power the Xiaomi 15 Pro in 2025. However,
>> Apple should regain its position as innovation
>> leader in 2026 with the release of the
>> iPhone 18, which should feature the A20
>> chip built on TSMC’s 2 nm process."
>>
>> But there is a vertical vias revolution
>> going on as well, some SOCs typically
>> being at 18 layers now:
>>
>> Zooming Into a CPU (It's Incredible)
>> https://www.youtube.com/watch?v=Bez-2cvYja0
>>
>> imec has coined the term CMOS 2.0:
>>
>> LEUVEN (Belgium), MARCH 12th, 2026 — Imec,
>> a world-leading research and innovation hub
>> in advanced semiconductor technologies, has
>> launched a first-of-its-kind consortium with
>> 26 European university groups that will jointly
>> work on the technology roadmap beyond
>> CMOS scaling (CMOS 2.0).
>> https://www.imec-int.com/en/press/imec-launches-university-consortium-around-next-generation-chips 
>>
>>
>> So we might see more mobile grade GPUs.
>>
>> Bye
> 

[toc] | [prev] | [next] | [standalone]

#15632 — Light Tuning of LLMs Locally (Was: Micro penis walking around with a rucksack)

Hi,

Interestingly  "Strix" (Strix Point) is no longer
the top news, as "Krackan" (Krackan Point) and the
massive "Halo" (Strix Halo) have officially stepped
into the spotlight.

The New AMD Ryzen Ai Halo Mini PC Has The Most Powerful iGPU!
https://www.youtube.com/watch?v=AZpCPX_EJPg

My tester Acer Swift Go was already "Krackan" (Krackan
Point. So a shift from local inferencing, to limited
local machine learning is possible. And AMD
Ryzen is hitting the drums:

AMD Ryzen™ AI Halo: Build the AI You Want. Your Stack. Your Rules.
https://www.youtube.com/watch?v=lxTaJ5LDY20

Pre-orders for the platform open in June, featuring
128GB of unified memory which enables developers to
run intensive workloads with models up to 200
billion parameters.

LoL

Have Fun!

Bye

Mild Shock schrieb:
> Hi,
> 
> So we might see more mobile grade GPUs,
> on a finger nail, without any cooling fans
> in the future? Yes my Redmi smart phone doesn't
> 
> have any cooling fans, I do not intend to put
> a RTX 5090 in a rucksack and carry a 600 W battery
> pack (*), to have some AI on my phone.
> 
> Have Fun!
> 
> Bye
> 
> (*) The Bluetti Premium 30 V2 is 4.3 Kg heavy:
> https://www.galaxus.ch/de/s4/product/bluetti-premium-30-v2-320-wh-430-kg-power-station-65489839 
> 
> 
> Mirco penis was loosing his marbles:
>> you stinking sack of rocks, you can't read your own redundant links. 
>> Watch the prices for the
>  > Ryzen AI laptops. Fucking idiot. Not worth the
>  > price for what they give in AI. Those are embedded
>  > cpu/gpu cretin, you don't need to read more.
> 
> Mild Shock schrieb:
>> Hi,
>>
>> For marketing purposes people
>> typically look at the race towards
>> 2nm, and we find:
>>
>> A month ago, Apple lost its exclusivity
>> on 3 nm smartphone processors with
>> MediaTek’s Dimensity 9400 chip, integrated
>> in the Vivo X200 Pro smartphone. Qualcomm
>> is also in the race with its recently
>> unveiled Snapdragon 8 Elite and set to
>> power the Xiaomi 15 Pro in 2025. However,
>> Apple should regain its position as innovation
>> leader in 2026 with the release of the
>> iPhone 18, which should feature the A20
>> chip built on TSMC’s 2 nm process."
>>
>> But there is a vertical vias revolution
>> going on as well, some SOCs typically
>> being at 18 layers now:
>>
>> Zooming Into a CPU (It's Incredible)
>> https://www.youtube.com/watch?v=Bez-2cvYja0
>>
>> imec has coined the term CMOS 2.0:
>>
>> LEUVEN (Belgium), MARCH 12th, 2026 — Imec,
>> a world-leading research and innovation hub
>> in advanced semiconductor technologies, has
>> launched a first-of-its-kind consortium with
>> 26 European university groups that will jointly
>> work on the technology roadmap beyond
>> CMOS scaling (CMOS 2.0).
>> https://www.imec-int.com/en/press/imec-launches-university-consortium-around-next-generation-chips 
>>
>>
>> So we might see more mobile grade GPUs.
>>
>> Bye
> 

[toc] | [prev] | [next] | [standalone]

#15634 — PCIe 6.0 x16 versus LPDDR5X-8000 latency (Re: Light Tuning of LLMs Locally)

Hi,

Its amazing how Micro Penis slumps in
his own turf, when he argues against iGPU
via nonsense like:

 > to the embedded gpu, blocked by the speed of the cpu

Facts are that dual channel RAM has some
advantage over PCIe x16. Take for example latency:

Latency Comparison

Data Pathway  Approximate Latency   Why It Matters
iGPU to LPDDR5X-8000  ~30 to 50 ns
Direct on-die access. The iGPU accesses the system
RAM directly through the CPU's internal fabric,
bypassing the PCIe bus completely.

GPU over PCIe 6.0 x4 Link ~80 to 100 ns
Bus transition penalty. This is just the time it
takes for a packet to leave the GPU chip, travel
down 4 traces, and reach the system controller.

For PCIe 6.0 x16 latency is a little lower,
but still higher than LPDDR5X-8000.

Bye

Mild Shock schrieb:
> Hi,
> 
> Interestingly  "Strix" (Strix Point) is no longer
> the top news, as "Krackan" (Krackan Point) and the
> massive "Halo" (Strix Halo) have officially stepped
> into the spotlight.
> 
> The New AMD Ryzen Ai Halo Mini PC Has The Most Powerful iGPU!
> https://www.youtube.com/watch?v=AZpCPX_EJPg
> 
> My tester Acer Swift Go was already "Krackan" (Krackan
> Point. So a shift from local inferencing, to limited
> local machine learning is possible. And AMD
> Ryzen is hitting the drums:
> 
> AMD Ryzen™ AI Halo: Build the AI You Want. Your Stack. Your Rules.
> https://www.youtube.com/watch?v=lxTaJ5LDY20
> 
> Pre-orders for the platform open in June, featuring
> 128GB of unified memory which enables developers to
> run intensive workloads with models up to 200
> billion parameters.
> 
> LoL
> 
> Have Fun!
> 
> Bye
> 
> Mild Shock schrieb:
>> Hi,
>>
>> So we might see more mobile grade GPUs,
>> on a finger nail, without any cooling fans
>> in the future? Yes my Redmi smart phone doesn't
>>
>> have any cooling fans, I do not intend to put
>> a RTX 5090 in a rucksack and carry a 600 W battery
>> pack (*), to have some AI on my phone.
>>
>> Have Fun!
>>
>> Bye
>>
>> (*) The Bluetti Premium 30 V2 is 4.3 Kg heavy:
>> https://www.galaxus.ch/de/s4/product/bluetti-premium-30-v2-320-wh-430-kg-power-station-65489839 
>>
>>
>> Mirco penis was loosing his marbles:
>>> you stinking sack of rocks, you can't read your own redundant links. 
>>> Watch the prices for the
>>  > Ryzen AI laptops. Fucking idiot. Not worth the
>>  > price for what they give in AI. Those are embedded
>>  > cpu/gpu cretin, you don't need to read more.
>>
>> Mild Shock schrieb:
>>> Hi,
>>>
>>> For marketing purposes people
>>> typically look at the race towards
>>> 2nm, and we find:
>>>
>>> A month ago, Apple lost its exclusivity
>>> on 3 nm smartphone processors with
>>> MediaTek’s Dimensity 9400 chip, integrated
>>> in the Vivo X200 Pro smartphone. Qualcomm
>>> is also in the race with its recently
>>> unveiled Snapdragon 8 Elite and set to
>>> power the Xiaomi 15 Pro in 2025. However,
>>> Apple should regain its position as innovation
>>> leader in 2026 with the release of the
>>> iPhone 18, which should feature the A20
>>> chip built on TSMC’s 2 nm process."
>>>
>>> But there is a vertical vias revolution
>>> going on as well, some SOCs typically
>>> being at 18 layers now:
>>>
>>> Zooming Into a CPU (It's Incredible)
>>> https://www.youtube.com/watch?v=Bez-2cvYja0
>>>
>>> imec has coined the term CMOS 2.0:
>>>
>>> LEUVEN (Belgium), MARCH 12th, 2026 — Imec,
>>> a world-leading research and innovation hub
>>> in advanced semiconductor technologies, has
>>> launched a first-of-its-kind consortium with
>>> 26 European university groups that will jointly
>>> work on the technology roadmap beyond
>>> CMOS scaling (CMOS 2.0).
>>> https://www.imec-int.com/en/press/imec-launches-university-consortium-around-next-generation-chips 
>>>
>>>
>>> So we might see more mobile grade GPUs.
>>>
>>> Bye
>>
> 

[toc] | [prev] | [next] | [standalone]

#15635 — TSMC's 2nm (N2) node and the 7 GHz target (Re: Creating a "European CMOS 2.0 Army")

Hi,

TSMC's 2nm (N2) node and the 7 GHz target
represent a monumental milestone in silicon
manufacturing, shifting away from legacy
FinFETs to advanced Gate-All-Around (GAA)
nanosheet transistors.

This evolution allows chip designers—particularly
in the PC and AI sectors—to push processor
clock speeds previously thought impossible
on standard nodes

AMD confirms Zen 6 rollout for its July 22 AI event
https://videocardz.com/newz/amd-confirms-zen-6-launches-in-less-than-two-weeks-starting-with-epyc-venice

Production of the 6th Gen EPYC family is
already ramping up. AMD says Venice is its
first high-performance computing product
manufactured using TSMC’s 2nm process
technology.

Bye

Mild Shock schrieb:
> Hi,
> 
> For marketing purposes people
> typically look at the race towards
> 2nm, and we find:
> 
> A month ago, Apple lost its exclusivity
> on 3 nm smartphone processors with
> MediaTek’s Dimensity 9400 chip, integrated
> in the Vivo X200 Pro smartphone. Qualcomm
> is also in the race with its recently
> unveiled Snapdragon 8 Elite and set to
> power the Xiaomi 15 Pro in 2025. However,
> Apple should regain its position as innovation
> leader in 2026 with the release of the
> iPhone 18, which should feature the A20
> chip built on TSMC’s 2 nm process."
> 
> But there is a vertical vias revolution
> going on as well, some SOCs typically
> being at 18 layers now:
> 
> Zooming Into a CPU (It's Incredible)
> https://www.youtube.com/watch?v=Bez-2cvYja0
> 
> imec has coined the term CMOS 2.0:
> 
> LEUVEN (Belgium), MARCH 12th, 2026 — Imec,
> a world-leading research and innovation hub
> in advanced semiconductor technologies, has
> launched a first-of-its-kind consortium with
> 26 European university groups that will jointly
> work on the technology roadmap beyond
> CMOS scaling (CMOS 2.0).
> https://www.imec-int.com/en/press/imec-launches-university-consortium-around-next-generation-chips 
> 
> 
> So we might see more mobile grade GPUs.
> 
> Bye

[toc] | [prev] | [next] | [standalone]

#15637 — pi-WAM is just like Laika3, the first Dog on Mars (Was: TSMC's 2nm (N2) node and the 7 GHz target)

Hi,

We recently implemented a parallel π-WAM
on a GPU backend and could demonstrate an
estimated 11.4 Giga Lips. In this post we
report a further experiment, this time
presenting a parallel π-WAM on a CPU backend,
that can lift specialized Prolog, currently
to 1.7 Giga Lips performance.

Having an excess number of threads is a
bad idea. What if we do context switching
on our own? With this approach we could
bring down the execution time of 128 Hack
VMs by 33%. We estimate for the test which
had 11.4 GLips on the GPU, that we reach
1.7 GLips on the CPU.

Bye

See also:

Parallel π-WAM: 1.7 Giga Lips on a CPU
https://medium.com/2989/8a984e75af44

Mild Shock schrieb:
> Hi,
> 
> TSMC's 2nm (N2) node and the 7 GHz target
> represent a monumental milestone in silicon
> manufacturing, shifting away from legacy
> FinFETs to advanced Gate-All-Around (GAA)
> nanosheet transistors.
> 
> This evolution allows chip designers—particularly
> in the PC and AI sectors—to push processor
> clock speeds previously thought impossible
> on standard nodes
> 
> AMD confirms Zen 6 rollout for its July 22 AI event
> https://videocardz.com/newz/amd-confirms-zen-6-launches-in-less-than-two-weeks-starting-with-epyc-venice 
> 
> 
> Production of the 6th Gen EPYC family is
> already ramping up. AMD says Venice is its
> first high-performance computing product
> manufactured using TSMC’s 2nm process
> technology.
> 
> Bye
> 
> Mild Shock schrieb:
>> Hi,
>>
>> For marketing purposes people
>> typically look at the race towards
>> 2nm, and we find:
>>
>> A month ago, Apple lost its exclusivity
>> on 3 nm smartphone processors with
>> MediaTek’s Dimensity 9400 chip, integrated
>> in the Vivo X200 Pro smartphone. Qualcomm
>> is also in the race with its recently
>> unveiled Snapdragon 8 Elite and set to
>> power the Xiaomi 15 Pro in 2025. However,
>> Apple should regain its position as innovation
>> leader in 2026 with the release of the
>> iPhone 18, which should feature the A20
>> chip built on TSMC’s 2 nm process."
>>
>> But there is a vertical vias revolution
>> going on as well, some SOCs typically
>> being at 18 layers now:
>>
>> Zooming Into a CPU (It's Incredible)
>> https://www.youtube.com/watch?v=Bez-2cvYja0
>>
>> imec has coined the term CMOS 2.0:
>>
>> LEUVEN (Belgium), MARCH 12th, 2026 — Imec,
>> a world-leading research and innovation hub
>> in advanced semiconductor technologies, has
>> launched a first-of-its-kind consortium with
>> 26 European university groups that will jointly
>> work on the technology roadmap beyond
>> CMOS scaling (CMOS 2.0).
>> https://www.imec-int.com/en/press/imec-launches-university-consortium-around-next-generation-chips 
>>
>>
>> So we might see more mobile grade GPUs.
>>
>> Bye
> 

[toc] | [prev] | [next] | [standalone]

#15638 — So memory bandwidth is no issue at all (Re: pi-WAM is just like Laika3, the first Dog on Mars)

Hi,

So memory bandwidth is no issue at all for
this kind of backtracking problem. Its all
about arithmetic bandwidth . And since I am

not using vectors or matrices, it is still
poor. You can do the math. The CPU has 16
logical cores (8 physical with hyperthreading).

The GPU single-threaded is around 5 times
slower than the CPU single threaded, but
their number is greater. Now you can do

the math as follows:

16 * 11.4 / 1.7 * 5 = 536.47

Pretty much the number of shader cores (*),
i.e. 512, that the Ryzen AI 7 350 laptop
offers in its integrated GPU Radeon 860M.

LoL

Bye

(*) Unified shading units (also referred to
as unified shaders, shader cores, or stream
processors) are flexible processing components

inside a graphics processing unit (GPU) that
can handle any type of rendering or compute task.

Mild Shock schrieb:
> Hi,
> 
> We recently implemented a parallel π-WAM
> on a GPU backend and could demonstrate an
> estimated 11.4 Giga Lips. In this post we
> report a further experiment, this time
> presenting a parallel π-WAM on a CPU backend,
> that can lift specialized Prolog, currently
> to 1.7 Giga Lips performance.
> 
> Having an excess number of threads is a
> bad idea. What if we do context switching
> on our own? With this approach we could
> bring down the execution time of 128 Hack
> VMs by 33%. We estimate for the test which
> had 11.4 GLips on the GPU, that we reach
> 1.7 GLips on the CPU.
> 
> Bye
> 
> See also:
> 
> Parallel π-WAM: 1.7 Giga Lips on a CPU
> https://medium.com/2989/8a984e75af44
> 
> Mild Shock schrieb:
>> Hi,
>>
>> TSMC's 2nm (N2) node and the 7 GHz target
>> represent a monumental milestone in silicon
>> manufacturing, shifting away from legacy
>> FinFETs to advanced Gate-All-Around (GAA)
>> nanosheet transistors.
>>
>> This evolution allows chip designers—particularly
>> in the PC and AI sectors—to push processor
>> clock speeds previously thought impossible
>> on standard nodes
>>
>> AMD confirms Zen 6 rollout for its July 22 AI event
>> https://videocardz.com/newz/amd-confirms-zen-6-launches-in-less-than-two-weeks-starting-with-epyc-venice 
>>
>>
>> Production of the 6th Gen EPYC family is
>> already ramping up. AMD says Venice is its
>> first high-performance computing product
>> manufactured using TSMC’s 2nm process
>> technology.
>>
>> Bye
>>
>> Mild Shock schrieb:
>>> Hi,
>>>
>>> For marketing purposes people
>>> typically look at the race towards
>>> 2nm, and we find:
>>>
>>> A month ago, Apple lost its exclusivity
>>> on 3 nm smartphone processors with
>>> MediaTek’s Dimensity 9400 chip, integrated
>>> in the Vivo X200 Pro smartphone. Qualcomm
>>> is also in the race with its recently
>>> unveiled Snapdragon 8 Elite and set to
>>> power the Xiaomi 15 Pro in 2025. However,
>>> Apple should regain its position as innovation
>>> leader in 2026 with the release of the
>>> iPhone 18, which should feature the A20
>>> chip built on TSMC’s 2 nm process."
>>>
>>> But there is a vertical vias revolution
>>> going on as well, some SOCs typically
>>> being at 18 layers now:
>>>
>>> Zooming Into a CPU (It's Incredible)
>>> https://www.youtube.com/watch?v=Bez-2cvYja0
>>>
>>> imec has coined the term CMOS 2.0:
>>>
>>> LEUVEN (Belgium), MARCH 12th, 2026 — Imec,
>>> a world-leading research and innovation hub
>>> in advanced semiconductor technologies, has
>>> launched a first-of-its-kind consortium with
>>> 26 European university groups that will jointly
>>> work on the technology roadmap beyond
>>> CMOS scaling (CMOS 2.0).
>>> https://www.imec-int.com/en/press/imec-launches-university-consortium-around-next-generation-chips 
>>>
>>>
>>> So we might see more mobile grade GPUs.
>>>
>>> Bye
>>
> 

[toc] | [prev] | [next] | [standalone]

#15640 — For iGPU which acts as a APU RAM is shared (Re: So memory bandwidth is no issue at all)

Hi,

For iGPU which acts as a APU RAM is shared,

an integrated GPU (iGPU) used as an APU
relies entirely on shared system RAM.
Because the processor and graphics chip
live on the same silicon die, they do not
have their own separate video memory
(like discrete GPUs do with dedicated VRAM).
Instead, the iGPU carves out a portion of
your regular system memory to store textures,
frame buffers, and other graphics data.

While AMD originally coined Accelerated
Processing Unit (APU) in 2011 to highlight the
fusion of CPU and GPU on a single die,
modern AI computing has redefined what
it means to "accelerate" data. When Intel
and Apple discuss their latest processors,
they frequently highlight dedicated hardware
blocks called NPUs (Neural Processing Units) or
Neural Engines right alongside the CPU and GPU.

https://www.articsledge.com/post/accelerated-processing-unit-apu

Bye

Mild Shock schrieb:
> Hi,
> 
> So memory bandwidth is no issue at all for
> this kind of backtracking problem. Its all
> about arithmetic bandwidth . And since I am
> 
> not using vectors or matrices, it is still
> poor. You can do the math. The CPU has 16
> logical cores (8 physical with hyperthreading).
> 
> The GPU single-threaded is around 5 times
> slower than the CPU single threaded, but
> their number is greater. Now you can do
> 
> the math as follows:
> 
> 16 * 11.4 / 1.7 * 5 = 536.47
> 
> Pretty much the number of shader cores (*),
> i.e. 512, that the Ryzen AI 7 350 laptop
> offers in its integrated GPU Radeon 860M.
> 
> LoL
> 
> Bye
> 
> (*) Unified shading units (also referred to
> as unified shaders, shader cores, or stream
> processors) are flexible processing components
> 
> inside a graphics processing unit (GPU) that
> can handle any type of rendering or compute task.
> 
> Mild Shock schrieb:
>> Hi,
>>
>> We recently implemented a parallel π-WAM
>> on a GPU backend and could demonstrate an
>> estimated 11.4 Giga Lips. In this post we
>> report a further experiment, this time
>> presenting a parallel π-WAM on a CPU backend,
>> that can lift specialized Prolog, currently
>> to 1.7 Giga Lips performance.
>>
>> Having an excess number of threads is a
>> bad idea. What if we do context switching
>> on our own? With this approach we could
>> bring down the execution time of 128 Hack
>> VMs by 33%. We estimate for the test which
>> had 11.4 GLips on the GPU, that we reach
>> 1.7 GLips on the CPU.
>>
>> Bye
>>
>> See also:
>>
>> Parallel π-WAM: 1.7 Giga Lips on a CPU
>> https://medium.com/2989/8a984e75af44
>>
>> Mild Shock schrieb:
>>> Hi,
>>>
>>> TSMC's 2nm (N2) node and the 7 GHz target
>>> represent a monumental milestone in silicon
>>> manufacturing, shifting away from legacy
>>> FinFETs to advanced Gate-All-Around (GAA)
>>> nanosheet transistors.
>>>
>>> This evolution allows chip designers—particularly
>>> in the PC and AI sectors—to push processor
>>> clock speeds previously thought impossible
>>> on standard nodes
>>>
>>> AMD confirms Zen 6 rollout for its July 22 AI event
>>> https://videocardz.com/newz/amd-confirms-zen-6-launches-in-less-than-two-weeks-starting-with-epyc-venice 
>>>
>>>
>>> Production of the 6th Gen EPYC family is
>>> already ramping up. AMD says Venice is its
>>> first high-performance computing product
>>> manufactured using TSMC’s 2nm process
>>> technology.
>>>
>>> Bye
>>>
>>> Mild Shock schrieb:
>>>> Hi,
>>>>
>>>> For marketing purposes people
>>>> typically look at the race towards
>>>> 2nm, and we find:
>>>>
>>>> A month ago, Apple lost its exclusivity
>>>> on 3 nm smartphone processors with
>>>> MediaTek’s Dimensity 9400 chip, integrated
>>>> in the Vivo X200 Pro smartphone. Qualcomm
>>>> is also in the race with its recently
>>>> unveiled Snapdragon 8 Elite and set to
>>>> power the Xiaomi 15 Pro in 2025. However,
>>>> Apple should regain its position as innovation
>>>> leader in 2026 with the release of the
>>>> iPhone 18, which should feature the A20
>>>> chip built on TSMC’s 2 nm process."
>>>>
>>>> But there is a vertical vias revolution
>>>> going on as well, some SOCs typically
>>>> being at 18 layers now:
>>>>
>>>> Zooming Into a CPU (It's Incredible)
>>>> https://www.youtube.com/watch?v=Bez-2cvYja0
>>>>
>>>> imec has coined the term CMOS 2.0:
>>>>
>>>> LEUVEN (Belgium), MARCH 12th, 2026 — Imec,
>>>> a world-leading research and innovation hub
>>>> in advanced semiconductor technologies, has
>>>> launched a first-of-its-kind consortium with
>>>> 26 European university groups that will jointly
>>>> work on the technology roadmap beyond
>>>> CMOS scaling (CMOS 2.0).
>>>> https://www.imec-int.com/en/press/imec-launches-university-consortium-around-next-generation-chips 
>>>>
>>>>
>>>> So we might see more mobile grade GPUs.
>>>>
>>>> Bye
>>>
>>
> 

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#15642 — Village Idiot wants 8088 back [Puting Troll] (Re: For iGPU which acts as a APU RAM is shared)

Hi,

Ha Ha, Village Idiot is Pissed and
wants his Intel 8088 back. There you
have boards with VRAM = 1k Byte.

Well it fits you, since you are
a putin payed troll. Typically russian
or belarus 9000 level stupid.

Bye

Bobauk Modenov schrieb:
 > Mild Shock wrote:
 >
 >> an integrated GPU (iGPU) used as an APU relies entirely on shared system
 >> RAM. Because the processor and graphics chip live on the same silicon
 >> die, they do not have their own separate video memory
 >
 > idiot, yet another thing you dont undrestand, only max half of the entire
 > ram can be given to the gpu. Most of the laptops gives even less, say max
 > 1 GB of the "shared" ram to the gpu. Idiot.
 >

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#15643 — VT100 25 x 80 terminal = 2000 Bytes (Re: Village Idiot wants 8088 back [Puting Troll])

Hi,

Ok i misscalculated the 1k Byes. For 25 x 80
ASCII characters it would be 2000 Bytes.
Sorry for the wrong adjustment of your VRAM.

BTW, a VT100 had indeed 3000 Bytes:

Released   1978
CPU    Intel 8080
Memory    3 KB RAM
https://en.wikipedia.org/wiki/VT100

So your 1GB were a little bit too high.
The lower bound is probably 2000 to
3000 bytes. Happy now moron?

Your 1GB were wroooong you were too
optimistic, in your pessimism.

Bye

Mild Shock schrieb:
> 
> Hi,
> 
> Ha Ha, Village Idiot is Pissed and
> wants his Intel 8088 back. There you
> have boards with VRAM = 1k Byte.
> 
> Well it fits you, since you are
> a putin payed troll. Typically russian
> or belarus 9000 level stupid.
> 
> Bye
> 
> Bobauk Modenov schrieb:
>  > Mild Shock wrote:
>  >
>  >> an integrated GPU (iGPU) used as an APU relies entirely on shared 
> system
>  >> RAM. Because the processor and graphics chip live on the same silicon
>  >> die, they do not have their own separate video memory
>  >
>  > idiot, yet another thing you dont undrestand, only max half of the 
> entire
>  > ram can be given to the gpu. Most of the laptops gives even less, say 
> max
>  > 1 GB of the "shared" ram to the gpu. Idiot.
>  >
> 

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#15894 — From short-cut parallelism to true parallelism [π-WAM Musings] (Re: pi-WAM is just like Laika3, the first Dog on Mars)

Hi,

The word Musings has a totally new meaning:

Torbjörn Lager wrote:
 > When
 >
 > call(Goal), Self ! Pid-Goal
 >
 > succeeds, that top-level goal has completed
 > and the actor terminates successfully.

Ok, I see. I thought it will be automatically
redone, and thus rapid fire multiple solutions.
So you have already hardwired a once/1 semantic
into your spawn/3, in that the spawn/3 goal argument

when executed, is onced, only looking at its EXIT
and FAIL port, not calling once more its REDO port.
This also means that both parallel/1 and
first_solution/1 have a short-cut AND

respective OR semantic:

/* AND-parallelism with short-cut */
parallel([G1,..,Gn])   <=>   once(G1), .., once(G2)

/* OR-parallelism with short-cut */
first_solution([G1,..,Gn])   <=>   once(G1); ..; once(G2)

The short-cut is in that parallel/1 can stop
at the first failure, and that first_solution/1
can stop at the first success. I wonder whether
Web Prolog Trinity offers true AND-parallelism or

true OR-parallelism without a short-cut. Having
such constructs could be interesting for problem
solving and is often used parallel search. For
example SICStus Prolog offers, or offered, true

OR-parallelism in its Multi-sequential Prolog
engines (Muse) extension, from the SICS experiments
in the 1990s with the BNN Butterfly supercomputer
from the 1980s:

yes
| ?- muse_flag(num_workers,_,5).
| ?- run.
724 solutions in 2.760 seconds.

yes
| ?- muse_flag(num_workers,_,1).
| ?- run.
724 solutions in 10.400 seconds.

https://sicstus.sics.se/sicstus/docs/3.7.1/html/sicstus_6.html

The intervention for true OR-paralleism is usually
at rule choice points. So when you have a set
of rules, like for example in the case of
the select/3 predicate:

select([X|Xs], Xs, X).
select([Y|Ys], [Y|Zs], X) :- select(Ys, Zs, X).

You execute it as:

select(X, Y, Z) :-
     muse([select1(X,Y,Z), select2(X,Y,Z)]).

select1([X|Xs], Xs, X).
select2([Y|Ys], [Y|Zs], X) :- select(Ys, Zs, X).

Where the muse meta predicate has true OR parallelism:

muse([G1,..,Gn])    <=>    G1 | .. | Gn

Bye

See also:

The muse approach to Or-parallel prolog
https://link.springer.com/article/10.1007/BF01407834

BBN Butterfly
https://en.wikipedia.org/wiki/BBN_Butterfly

P.S.: Maybe this explains my Freundlian slip when
I expected your parallel/1 to be some OR-parallelism,
while it is some AND-parallism. The true OR-parallelism

can be mathematically formalized in logic via
non-determinism and π-calculus:

π-calculus
https://ncatlab.org/nlab/show/pi-calculus

You even don’t need actor mailboxes, only channel objects.

Mild Shock schrieb:
> Hi,
> 
> We recently implemented a parallel π-WAM
> on a GPU backend and could demonstrate an
> estimated 11.4 Giga Lips. In this post we
> report a further experiment, this time
> presenting a parallel π-WAM on a CPU backend,
> that can lift specialized Prolog, currently
> to 1.7 Giga Lips performance.
> 
> Having an excess number of threads is a
> bad idea. What if we do context switching
> on our own? With this approach we could
> bring down the execution time of 128 Hack
> VMs by 33%. We estimate for the test which
> had 11.4 GLips on the GPU, that we reach
> 1.7 GLips on the CPU.
> 
> Bye
> 
> See also:
> 
> Parallel π-WAM: 1.7 Giga Lips on a CPU
> https://medium.com/2989/8a984e75af44
> 
> Mild Shock schrieb:
>> Hi,
>>
>> TSMC's 2nm (N2) node and the 7 GHz target
>> represent a monumental milestone in silicon
>> manufacturing, shifting away from legacy
>> FinFETs to advanced Gate-All-Around (GAA)
>> nanosheet transistors.
>>
>> This evolution allows chip designers—particularly
>> in the PC and AI sectors—to push processor
>> clock speeds previously thought impossible
>> on standard nodes
>>
>> AMD confirms Zen 6 rollout for its July 22 AI event
>> https://videocardz.com/newz/amd-confirms-zen-6-launches-in-less-than-two-weeks-starting-with-epyc-venice 
>>
>>
>> Production of the 6th Gen EPYC family is
>> already ramping up. AMD says Venice is its
>> first high-performance computing product
>> manufactured using TSMC’s 2nm process
>> technology.
>>
>> Bye
>>
>> Mild Shock schrieb:
>>> Hi,
>>>
>>> For marketing purposes people
>>> typically look at the race towards
>>> 2nm, and we find:
>>>
>>> A month ago, Apple lost its exclusivity
>>> on 3 nm smartphone processors with
>>> MediaTek’s Dimensity 9400 chip, integrated
>>> in the Vivo X200 Pro smartphone. Qualcomm
>>> is also in the race with its recently
>>> unveiled Snapdragon 8 Elite and set to
>>> power the Xiaomi 15 Pro in 2025. However,
>>> Apple should regain its position as innovation
>>> leader in 2026 with the release of the
>>> iPhone 18, which should feature the A20
>>> chip built on TSMC’s 2 nm process."
>>>
>>> But there is a vertical vias revolution
>>> going on as well, some SOCs typically
>>> being at 18 layers now:
>>>
>>> Zooming Into a CPU (It's Incredible)
>>> https://www.youtube.com/watch?v=Bez-2cvYja0
>>>
>>> imec has coined the term CMOS 2.0:
>>>
>>> LEUVEN (Belgium), MARCH 12th, 2026 — Imec,
>>> a world-leading research and innovation hub
>>> in advanced semiconductor technologies, has
>>> launched a first-of-its-kind consortium with
>>> 26 European university groups that will jointly
>>> work on the technology roadmap beyond
>>> CMOS scaling (CMOS 2.0).
>>> https://www.imec-int.com/en/press/imec-launches-university-consortium-around-next-generation-chips 
>>>
>>>
>>> So we might see more mobile grade GPUs.
>>>
>>> Bye
>>
> 

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#15895 — I think Erlang is completely dead. And I repeat it. (Was: From short-cut parallelism to true parallelism [π-WAM Musings])

Hi,

 > has alreay the meaning of Prolog REPL without
 > any actors. Moslikely its a strange view of
 > having a WASM somewhere? That does something
 > for you? I am really clueless what “toplevel”
 > should mean.

I think Erlang is completely dead. And I repeat it.
What you need to do is go back to WAM. Also state
charts are dead, WAM has switch instructions, it
can perfectly do state charts. Scryer Prolog

made some state chart tests:

Backtracking DCG vs DFA vs Rational Tree Automaton
https://github.com/mthom/scryer-prolog/discussions/3433https://github.com/mthom/scryer-prolog/discussions/3433#discussioncomment-18138834

What you need to investigate how SWI Prolog
can become again a WAM Prolog that can generate
WAM code. And that actors can also exchange
binary WAM code.

And spawn/1 will have a parameter to create
1000 actors or more instantly. And most of all
don’t use the word “actor” anymore, use the
word “agent”. Disclaimer: Of course

WAM is not the only option here. But in as
far, it seems am not the only one embracing GPU
with my π-WAM for Dogelog Player. Some big
companies like Palantir use

GPU for search .filter and aggregation
.group_by / .agg. Would be nice if one could
write Prolog, and ship it to a GPU ? What do
you think, you are at the source of actor

thinking, and that your brought state charts
into play makes you destined to have a broad
horizon that is needed to grok some things related
to the AI Boom which have nothing to do with LLM:

     result = (
         lf.with_columns(
             (pl.col("a") * pl.col("b")).alias("product"),
             (pl.col("a").pow(2) + pl.col("b").pow(2)).sqrt().alias("norm"),
         )
         .group_by("category")
         .agg(
             pl.col("product").sum().alias("total_product"),
             pl.col("norm").mean().alias("mean_norm"),
             pl.len().alias("n"),
         )
         .sort("total_product", descending=True)
     )
https://www.palantir.com/docs/foundry/transforms-python/advanced-compute#gpu-accelerated-polars-with-cudf

The speedup for a NIVIDIA B200 is amazing:

https://docs.rapids.ai/api/cudf/stable/cudf_polars/

Bye

Mild Shock schrieb:
> Hi,
> 
> The word Musings has a totally new meaning:
> 
> Torbjörn Lager wrote:
>  > When
>  >
>  > call(Goal), Self ! Pid-Goal
>  >
>  > succeeds, that top-level goal has completed
>  > and the actor terminates successfully.
> 
> Ok, I see. I thought it will be automatically
> redone, and thus rapid fire multiple solutions.
> So you have already hardwired a once/1 semantic
> into your spawn/3, in that the spawn/3 goal argument
> 
> when executed, is onced, only looking at its EXIT
> and FAIL port, not calling once more its REDO port.
> This also means that both parallel/1 and
> first_solution/1 have a short-cut AND
> 
> respective OR semantic:
> 
> /* AND-parallelism with short-cut */
> parallel([G1,..,Gn])   <=>   once(G1), .., once(G2)
> 
> /* OR-parallelism with short-cut */
> first_solution([G1,..,Gn])   <=>   once(G1); ..; once(G2)
> 
> The short-cut is in that parallel/1 can stop
> at the first failure, and that first_solution/1
> can stop at the first success. I wonder whether
> Web Prolog Trinity offers true AND-parallelism or
> 
> true OR-parallelism without a short-cut. Having
> such constructs could be interesting for problem
> solving and is often used parallel search. For
> example SICStus Prolog offers, or offered, true
> 
> OR-parallelism in its Multi-sequential Prolog
> engines (Muse) extension, from the SICS experiments
> in the 1990s with the BNN Butterfly supercomputer
> from the 1980s:
> 
> yes
> | ?- muse_flag(num_workers,_,5).
> | ?- run.
> 724 solutions in 2.760 seconds.
> 
> yes
> | ?- muse_flag(num_workers,_,1).
> | ?- run.
> 724 solutions in 10.400 seconds.
> 
> https://sicstus.sics.se/sicstus/docs/3.7.1/html/sicstus_6.html
> 
> The intervention for true OR-paralleism is usually
> at rule choice points. So when you have a set
> of rules, like for example in the case of
> the select/3 predicate:
> 
> select([X|Xs], Xs, X).
> select([Y|Ys], [Y|Zs], X) :- select(Ys, Zs, X).
> 
> You execute it as:
> 
> select(X, Y, Z) :-
>      muse([select1(X,Y,Z), select2(X,Y,Z)]).
> 
> select1([X|Xs], Xs, X).
> select2([Y|Ys], [Y|Zs], X) :- select(Ys, Zs, X).
> 
> Where the muse meta predicate has true OR parallelism:
> 
> muse([G1,..,Gn])    <=>    G1 | .. | Gn
> 
> Bye
> 
> See also:
> 
> The muse approach to Or-parallel prolog
> https://link.springer.com/article/10.1007/BF01407834
> 
> BBN Butterfly
> https://en.wikipedia.org/wiki/BBN_Butterfly
> 
> P.S.: Maybe this explains my Freundlian slip when
> I expected your parallel/1 to be some OR-parallelism,
> while it is some AND-parallism. The true OR-parallelism
> 
> can be mathematically formalized in logic via
> non-determinism and π-calculus:
> 
> π-calculus
> https://ncatlab.org/nlab/show/pi-calculus
> 
> You even don’t need actor mailboxes, only channel objects.
> 

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