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Groups > comp.lang.forth > #34459 > unrolled thread
| Started by | JUERGEN <epldfpga@aol.com> |
|---|---|
| First post | 2014-11-17 02:26 -0800 |
| Last post | 2014-11-21 15:42 -0800 |
| Articles | 20 on this page of 159 — 23 participants |
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http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? JUERGEN <epldfpga@aol.com> - 2014-11-17 02:26 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Paul E Bennett <Paul_E.Bennett@topmail.co.uk> - 2014-11-17 14:24 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? rickman <gnuarm@gmail.com> - 2014-11-17 14:04 -0500
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? visualforth@rocketmail.com - 2014-11-17 18:37 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? hughaguilar96@yahoo.com - 2014-11-17 19:58 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-18 04:56 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-11-18 19:10 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-18 14:06 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? the_gavino_himself <visphatesjava@gmail.com> - 2014-11-23 19:43 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? "Rod Pemberton" <buzzoff@nonamewhichexists.cmm> - 2014-11-18 16:16 -0500
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? visualforth@rocketmail.com - 2014-11-18 15:49 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? the_gavino_himself <visphatesjava@gmail.com> - 2014-11-23 19:45 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? rickman <gnuarm@gmail.com> - 2014-11-23 23:45 -0500
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? "Rod Pemberton" <buzzoff@nonamewhichexists.cmm> - 2014-11-24 17:18 -0500
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-23 14:04 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-23 11:25 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-24 09:36 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-24 06:02 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-24 13:04 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-11-24 14:50 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-24 14:06 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? "Alex McDonald" <blog@rivadpm.com> - 2014-11-24 16:38 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-24 09:04 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-24 16:16 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-24 12:57 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-25 16:18 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? rickman <gnuarm@gmail.com> - 2014-11-25 14:40 -0500
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-11-26 00:48 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? rickman <gnuarm@gmail.com> - 2014-11-25 19:10 -0500
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-11-26 02:09 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-26 11:22 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? rickman <gnuarm@gmail.com> - 2014-11-26 16:11 -0500
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Paul Rubin <no.email@nospam.invalid> - 2014-11-25 16:57 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-26 03:51 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-27 16:10 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-27 10:39 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-28 15:27 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-28 10:26 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-11-29 01:03 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-29 15:27 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-11-29 19:04 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-30 15:48 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-11-30 17:36 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-12-03 14:25 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? hughaguilar96@gmail.com - 2014-12-04 20:04 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-12-04 08:37 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-12-04 21:39 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-12-05 03:31 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-12-05 18:33 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-12-05 14:56 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? albert@spenarnc.xs4all.nl (Albert van der Horst) - 2014-11-29 13:07 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-29 16:00 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-29 11:21 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-30 15:26 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-30 12:49 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-11-24 18:34 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-25 16:04 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? rickman <gnuarm@gmail.com> - 2014-11-25 14:48 -0500
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? albert@spenarnc.xs4all.nl (Albert van der Horst) - 2014-11-26 00:49 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? rickman <gnuarm@gmail.com> - 2014-11-25 21:07 -0500
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-26 11:45 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Paul E Bennett <Paul_E.Bennett@topmail.co.uk> - 2014-11-26 12:44 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-26 14:11 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? rickman <gnuarm@gmail.com> - 2014-11-26 16:17 -0500
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-11-26 23:27 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-27 12:28 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-27 09:20 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-27 15:59 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-27 10:42 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-28 15:44 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-28 10:35 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-29 15:38 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-11-29 19:10 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-30 16:09 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-11-30 17:40 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-12-03 16:47 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-12-04 21:22 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-12-05 12:37 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-12-05 19:02 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-12-06 12:09 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? JUERGEN <epldfpga@aol.com> - 2014-12-06 06:45 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-12-06 19:58 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-12-07 13:39 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Paul Rubin <no.email@nospam.invalid> - 2014-12-07 08:04 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-12-07 22:52 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-12-10 12:46 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-12-11 02:08 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-12-11 10:20 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-12-11 05:06 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Jan Coombs <Jan-54 <jenfhaomndgfwutc@murmic.plus.com>> - 2014-12-11 17:56 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? "Alex McDonald" <blog@rivadpm.com> - 2014-12-15 15:57 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-12-16 07:53 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? JUERGEN <epldfpga@aol.com> - 2014-12-17 08:49 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-12-11 23:46 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Paul Rubin <no.email@nospam.invalid> - 2014-12-11 16:24 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Julian Fondren <julian.fondren@gmail.com> - 2014-12-11 17:46 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Paul Rubin <no.email@nospam.invalid> - 2014-12-11 22:20 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-12-13 00:24 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Paul Rubin <no.email@nospam.invalid> - 2014-12-12 18:39 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-12-13 21:06 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Paul Rubin <no.email@nospam.invalid> - 2014-12-13 22:58 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Mark Wills <markwills1970@gmail.com> - 2014-12-04 03:38 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Horse Shit <puke.aguilar@hughfailure.com> - 2014-12-04 13:29 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? JUERGEN <epldfpga@aol.com> - 2014-11-28 05:36 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-28 10:37 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-11-26 01:14 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Paul Rubin <no.email@nospam.invalid> - 2014-11-23 20:57 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-24 03:59 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Paul Rubin <no.email@nospam.invalid> - 2014-11-24 02:14 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-24 06:09 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Paul Rubin <no.email@nospam.invalid> - 2014-11-24 11:04 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? "Elizabeth D. Rather" <erather@forth.com> - 2014-11-24 11:49 -1000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Paul Rubin <no.email@nospam.invalid> - 2014-11-24 13:57 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? "Elizabeth D. Rather" <erather@forth.com> - 2014-11-24 12:28 -1000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Paul Rubin <no.email@nospam.invalid> - 2014-11-24 14:50 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? "Elizabeth D. Rather" <erather@forth.com> - 2014-11-24 13:22 -1000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Paul Rubin <no.email@nospam.invalid> - 2014-11-24 16:15 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? "Elizabeth D. Rather" <erather@forth.com> - 2014-11-24 14:38 -1000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-11-25 01:52 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-25 11:43 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-25 03:35 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Paul Rubin <no.email@nospam.invalid> - 2014-11-25 09:37 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-26 03:57 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-25 11:16 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? rickman <gnuarm@gmail.com> - 2014-11-25 02:06 -0500
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? "Elizabeth D. Rather" <erather@forth.com> - 2014-11-24 21:40 -1000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Paul Rubin <no.email@nospam.invalid> - 2014-11-24 23:57 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? rickman <gnuarm@gmail.com> - 2014-11-25 03:37 -0500
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-25 03:43 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? albert@spenarnc.xs4all.nl (Albert van der Horst) - 2014-11-25 15:26 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-25 15:47 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-25 03:30 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Paul Rubin <no.email@nospam.invalid> - 2014-11-25 09:32 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-25 11:11 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-24 12:24 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Paul Rubin <no.email@nospam.invalid> - 2014-11-25 09:45 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-24 10:17 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? rickman <gnuarm@gmail.com> - 2014-11-17 23:20 -0500
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Raimond Dragomir <raimond.dragomir@gmail.com> - 2014-11-17 23:31 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? rickman <gnuarm@gmail.com> - 2014-11-18 02:44 -0500
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Raimond Dragomir <raimond.dragomir@gmail.com> - 2014-11-18 00:18 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? albert@spenarnc.xs4all.nl (Albert van der Horst) - 2014-11-18 13:51 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? rickman <gnuarm@gmail.com> - 2014-11-18 12:06 -0500
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Elizabeth D Rather <erather@forth.com> - 2014-11-18 09:23 -1000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Paul Rubin <no.email@nospam.invalid> - 2014-11-18 08:09 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? rickman <gnuarm@gmail.com> - 2014-11-18 18:01 -0500
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Elizabeth D Rather <erather@forth.com> - 2014-11-17 21:58 -1000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? albert@spenarnc.xs4all.nl (Albert van der Horst) - 2014-11-18 14:04 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Bernd Paysan <bernd.paysan@gmx.de> - 2014-11-18 18:53 +0100
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Andrew Haley <andrew29@littlepinkcloud.invalid> - 2014-11-18 14:15 -0600
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-23 13:40 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? hughaguilar96@yahoo.com - 2014-11-18 17:48 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-23 14:24 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? albert@spenarnc.xs4all.nl (Albert van der Horst) - 2014-11-23 16:53 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? stephen@mpeforth.com (Stephen Pelc) - 2014-11-23 17:26 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? Mark Wills <markwills1970@gmail.com> - 2014-11-18 03:34 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? m.a.m.hendrix@tue.nl - 2014-11-18 04:19 -0800
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2014-11-23 13:50 +0000
Re: http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? visualforth@rocketmail.com - 2014-11-21 15:42 -0800
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| From | JUERGEN <epldfpga@aol.com> |
|---|---|
| Date | 2014-11-17 02:26 -0800 |
| Subject | http://www.lowrisc.org/ Open Core - is the Forth Community involved in this new 64Bit Core? |
| Message-ID | <38ce3d1c-72a5-45fc-8672-aa3ce52e9099@googlegroups.com> |
Is anybody here involved in thei project, to make them aware of requirements to run Forth efficiently? http://www.lowrisc.org/ From the website: lowRISC is producing fully open hardware systems. From the processor core to the development board, our goal is to create a completely open computing eco-system. Our open-source SoC (System-on-a-Chip) designs will be based on the 64-bit RISC-V instruction set architecture. Volume silicon manufacture is planned as is a low-cost development board. There are more details on our plans in these slides from a recent talk lowRISC is a not-for-profit organisation working closely with the University of Cambridge and the open-source community. To keep track of the project, follow @lowRISC or join our announcements list by entering your email below:
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| From | Paul E Bennett <Paul_E.Bennett@topmail.co.uk> |
|---|---|
| Date | 2014-11-17 14:24 +0000 |
| Message-ID | <ccueojFn3evU1@mid.individual.net> |
| In reply to | #34459 |
JUERGEN wrote: > Is anybody here involved in thei project, to make them aware of > requirements to run Forth efficiently? > > http://www.lowrisc.org/ > > From the website: > > lowRISC is producing fully open hardware systems. From the processor core > to the development board, our goal is to create a completely open > computing eco-system. > > Our open-source SoC (System-on-a-Chip) designs will be based on the 64-bit > RISC-V instruction set architecture. Volume silicon manufacture is planned > as is a low-cost development board. There are more details on our plans in > these slides from a recent talk > > lowRISC is a not-for-profit organisation working closely with the > University of Cambridge and the open-source community. > > To keep track of the project, follow @lowRISC or join our announcements > list by entering your email below: Looks rather more complex than processors like the RTX series or the B16. They seem to be aiming at the 64-bit end of the scale with a standard 32-bit instruction word which could include variable length instructions (16-bit and up depending on how you code the base end of the cell. -- ******************************************************************** Paul E. Bennett IEng MIET.....<email://Paul_E.Bennett@topmail.co.uk> Forth based HIDECS Consultancy.............<http://www.hidecs.co.uk> Mob: +44 (0)7811-639972 Tel: +44 (0)1235-510979 Going Forth Safely ..... EBA. www.electric-boat-association.org.uk.. ********************************************************************
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| From | rickman <gnuarm@gmail.com> |
|---|---|
| Date | 2014-11-17 14:04 -0500 |
| Message-ID | <m4dgsr$1cd$1@dont-email.me> |
| In reply to | #34463 |
On 11/17/2014 9:24 AM, Paul E Bennett wrote: > JUERGEN wrote: > >> Is anybody here involved in thei project, to make them aware of >> requirements to run Forth efficiently? >> >> http://www.lowrisc.org/ >> >> From the website: >> >> lowRISC is producing fully open hardware systems. From the processor core >> to the development board, our goal is to create a completely open >> computing eco-system. >> >> Our open-source SoC (System-on-a-Chip) designs will be based on the 64-bit >> RISC-V instruction set architecture. Volume silicon manufacture is planned >> as is a low-cost development board. There are more details on our plans in >> these slides from a recent talk >> >> lowRISC is a not-for-profit organisation working closely with the >> University of Cambridge and the open-source community. >> >> To keep track of the project, follow @lowRISC or join our announcements >> list by entering your email below: > > Looks rather more complex than processors like the RTX series or the B16. > They seem to be aiming at the 64-bit end of the scale with a standard 32-bit > instruction word which could include variable length instructions (16-bit > and up depending on how you code the base end of the cell. Yes, this is clearly not a MISC type processor. But they seem to be aiming high with intents to "commercialize" in the sense of producing chips that can compete against the present crop of ARMs used in most portable equipment. They may seem some significant use in some applications. I'm not sure it would be used much in highly competitive markets like cell phones or tablets. I think the whole profit motive will likely produce parts that always have an edge. Not entirely unlike the current state of the art in Forth compilers. There are tons of open source Forth tools, but if you have production type work you are better served paying for the commercial tools. But it just depends. If chip makers see this as a viable architecture it may end up getting a lot of support and use. One example of open source successfully taking on commercial products is the C compiler market. So what will make or break an open source CPU design? -- Rick
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| From | visualforth@rocketmail.com |
|---|---|
| Date | 2014-11-17 18:37 -0800 |
| Message-ID | <29c09bbe-60bb-4944-b78e-e461ea32c6b9@googlegroups.com> |
| In reply to | #34459 |
On Monday, November 17, 2014 5:26:05 AM UTC-5, JUERGEN wrote: > Is anybody here involved in their project, to make them aware of requirements to run Forth efficiently? > http://www.lowrisc.org/ Thanks for this information, Juergen. There is no connection to Forth at all. The CPU is planned as ISA, as seen in "The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.0" by Andrew Waterman, Yunsup Lee, David A. Patterson and Krste Asanović of the EECS Department, University of California, Berkeley, Technical Report No. UCB/EECS-2014-54, dated May 6, 2014. http://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-54.pdf I doubt that the lowRISC people will change their design to a multi-stack machine with zero cycle subroutine call and returns, even if they call themselves "OPEN TO THE CORE". 64 Bits would allow to have total control of the whole machine with each command. The ISA design allows this: VLIW encodings can be added as extensions using several alternative approaches. So it depends on the implementation by "lowRISC". But it is interesting that ISA has special standard extensions for Integer Multiplication and Division, Atomic Instructions, Single-Precision Floating-Point, Double-Precision Floating-Point, and Quad-Precision Floating-Point. Reminds me on all these special operations in Forth. But their Decimal Floating-Point doesn't fit. Interesting is the discussion "Why develop a new ISA?". It's a pity that Chuck's work is missing there. It's a architecture designed by a comittee. One argument is "Popular commercial ISAs are complex. The dominant commercial ISAs (x86 and ARM) are both very complex to implement in hardware to the level of supporting common software stacks and operating systems. Worse, nearly all the complexity is due to bad, or at least outdated, ISA design decisions rather than features that truly improve efficiency." Source: http://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-54.pdf Seems to be they skipped the chapter of stack machines in McClusky's "Design of Digital Computers". May be there is still time to tell those people that it would be a great idea to incorporate a data stack! Sources: https://aspire.eecs.berkeley.edu/2014/05/final-risc-v-user-level-isa-standard-released/ http://hackaday.io/project/2816-risc-v-instruction-set-architecture A ZedBoard and a Zybo board containing Xilinx Zynq chips and an ARM processor are available for evaluation/simulation.
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| From | hughaguilar96@yahoo.com |
|---|---|
| Date | 2014-11-17 19:58 -0800 |
| Message-ID | <a118f489-c1a5-457b-ae7f-9c7dbeeade8f@googlegroups.com> |
| In reply to | #34471 |
On Monday, November 17, 2014 7:37:34 PM UTC-7, visua...@rocketmail.com wrote: > One argument is "Popular commercial ISAs are complex. What I have found regarding the x86, is that nobody really knows what it is doing under the hood. Every implementation compiles the ultra-cisc x86 code (which is almost like a high-level language) into an internal risc code on the fly, but none of the chip makers will tell anybody anything about this internal code because it is proprietary. The result is that x86 assembly-language programming is similar to voodoo --- the priests have rituals that they use that supposedly result in fast code (most of the rituals provided by the painfully vague Volume-2 optimization book), but nobody knows whether the rituals actually work or, if they do work, how well they work, or what effect they have on each other when used together. The x86 is not just "complex" --- it is a black-box --- so I'm definitely interested in an open-source processor, just so I can know what is going on, like I did in the good old days. The Pentium with its U and V pipes was the last x86 that was understandable, and for which a person could write code that he knew would be optimal --- now "optimization" is done entirely by guess and by golly.
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| From | Andrew Haley <andrew29@littlepinkcloud.invalid> |
|---|---|
| Date | 2014-11-18 04:56 -0600 |
| Message-ID | <y92dnUUop996uPbJnZ2dnUU7-UudnZ2d@supernews.com> |
| In reply to | #34471 |
visualforth@rocketmail.com wrote: > On Monday, November 17, 2014 5:26:05 AM UTC-5, JUERGEN wrote: >> Is anybody here involved in their project, to make them aware of requirements to run Forth efficiently? >> http://www.lowrisc.org/ > One argument is "Popular commercial ISAs are complex. The dominant > commercial ISAs (x86 and ARM) are both very complex to implement in > hardware to the level of supporting common software stacks and > operating systems. Worse, nearly all the complexity is due to bad, > or at least outdated, ISA design decisions rather than features that > truly improve efficiency." > Source: http://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-54.pdf > > Seems to be they skipped the chapter of stack machines in McClusky's > "Design of Digital Computers". One of the architects is David Patterson -- who actually invented the term RISC -- so I think that idea that anyone "skipped the chapter" is ridiculous. It looks like quite a good design, in general: very conservative and only uses well-tried principles. I very much like the lack of condition codes. I don't like the load and store instructions, which seem to be missing some addressing modes you need to generate decent code: it seems there is only base+offset addressing. I may have misread the ISA, but I don't think so. Andrew.
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| From | Bernd Paysan <bernd.paysan@gmx.de> |
|---|---|
| Date | 2014-11-18 19:10 +0100 |
| Message-ID | <m4g21u$fqh$1@dont-email.me> |
| In reply to | #34481 |
Andrew Haley wrote: > It looks like quite a good design, in general: very conservative and > only uses well-tried principles. I very much like the lack of > condition codes. I don't like the load and store instructions, which > seem to be missing some addressing modes you need to generate decent > code: it seems there is only base+offset addressing. I may have > misread the ISA, but I don't think so. I miss an opcode table which would condense the information so that you can quickly identify if you missed something. I only see a load rd, (rs+offset) and a store (rd+offset), rs instruction, too; I also miss rotate instructions (needed for many modern crypto cores). The "you can synthesize a rotate out of two shifts and an or" doesn't count, because you need the speed - if you have crypto half as fast as on the next processor, because you are missing the rotate, you get half as much bandwidth with a fully encrypted network protocol. Implementing a barrel shifter with a rotate operation and a mask allows to implement left and right shifts (masks inverted to each other) and rotate (no mask) in the same piece of hardware. -- Bernd Paysan "If you want it done right, you have to do it yourself" http://bernd-paysan.de/
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| From | Andrew Haley <andrew29@littlepinkcloud.invalid> |
|---|---|
| Date | 2014-11-18 14:06 -0600 |
| Message-ID | <P6udnaPUh9dXO_bJnZ2dnUU7-I2dnZ2d@supernews.com> |
| In reply to | #34493 |
Bernd Paysan <bernd.paysan@gmx.de> wrote: > I also miss rotate instructions (needed for many modern crypto > cores). The "you can synthesize a rotate out of two shifts and an > or" doesn't count, because you need the speed - if you have crypto > half as fast as on the next processor, because you are missing the > rotate, you get half as much bandwidth with a fully encrypted > network protocol. Implementing a barrel shifter with a rotate > operation and a mask allows to implement left and right shifts > (masks inverted to each other) and rotate (no mask) in the same > piece of hardware. This is something that AArch64 does really well. Signed and unsigned bitfield moves (of which left and right shifts are special cases) and a two-word extract which works like this: EXTR Xd, Xn, Xm, #lsb Xd = Xn:Xm<lsb+63,lsb>. So, shifting an N-word integer takes N instructions regardless of the shift distance. ROR Xd, Xm, #uimm is an alias for EXTR Xd,Xm,Xm,#uimm. Andrew.
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| From | the_gavino_himself <visphatesjava@gmail.com> |
|---|---|
| Date | 2014-11-23 19:43 -0800 |
| Message-ID | <6d8fb079-b55a-44d8-a05b-c55ed6f677a9@googlegroups.com> |
| In reply to | #34493 |
On Tuesday, November 18, 2014 1:10:20 PM UTC-5, Bernd Paysan wrote: > Andrew Haley wrote: > > It looks like quite a good design, in general: very conservative and > > only uses well-tried principles. I very much like the lack of > > condition codes. I don't like the load and store instructions, which > > seem to be missing some addressing modes you need to generate decent > > code: it seems there is only base+offset addressing. I may have > > misread the ISA, but I don't think so. > > I miss an opcode table which would condense the information so that you can > quickly identify if you missed something. I only see a load rd, (rs+offset) > and a store (rd+offset), rs instruction, too; I also miss rotate > instructions (needed for many modern crypto cores). The "you can synthesize > a rotate out of two shifts and an or" doesn't count, because you need the > speed - if you have crypto half as fast as on the next processor, because > you are missing the rotate, you get half as much bandwidth with a fully > encrypted network protocol. Implementing a barrel shifter with a rotate > operation and a mask allows to implement left and right shifts (masks > inverted to each other) and rotate (no mask) in the same piece of hardware. > > -- > Bernd Paysan > "If you want it done right, you have to do it yourself" > http://bernd-paysan.de/ Where did you learn to design cpu?
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| From | "Rod Pemberton" <buzzoff@nonamewhichexists.cmm> |
|---|---|
| Date | 2014-11-18 16:16 -0500 |
| Message-ID | <op.xpjheas8mk81un@localhost> |
| In reply to | #34481 |
On Tue, 18 Nov 2014 05:56:39 -0500, Andrew Haley <andrew29@littlepinkcloud.invalid> wrote: > visualforth@rocketmail.com wrote: >> On Monday, November 17, 2014 5:26:05 AM UTC-5, JUERGEN wrote: >>> Is anybody here involved in their project, to make them aware of >>> requirements to run Forth efficiently? >>> >> One argument is "Popular commercial ISAs are complex. The dominant >> commercial ISAs (x86 and ARM) are both very complex to implement in >> hardware to the level of supporting common software stacks and >> operating systems. Worse, nearly all the complexity is due to bad, >> or at least outdated, ISA design decisions rather than features that >> truly improve efficiency." >> >> Seems to be they skipped the chapter of stack machines in McClusky's >> "Design of Digital Computers". > > One of the architects is David Patterson -- who actually invented the > term RISC -- so I think that idea that anyone "skipped the chapter" is > ridiculous. > Did anyone here _actually_ read the linked to overview of the RISC-V instruction set they're using? "Optional variable-length instructions to both expand available instruction encoding space and to support an optional dense instruction encoding for improved performance, static code size, and energy efficiency." http://riscv.org/ So, that's VLIW and CISC *plus* RISC, all in one package. I can't see how that's much different from modern x86, if any. As an open design, the very first thing it's going to get is an open, standardized set of CISC instructions ... You can pretty much guarantee that due to human nature. Now, it seems, we have a RISC pioneer supporting both CISC and VLIW. Amazing! I'd say he _clearly_ *missed* something. Maybe, he missed having some CISC instructions during his first time around with RISC. LOL. As people look for new solutions to old problems, they inevitably recycle old solutions and call them new. First, it was the MILL architecture, now it's lowRISC. What's next? A 1024-bit PDP-11? A 1Thz 6502? Z80E9? Rod Pemberton
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| From | visualforth@rocketmail.com |
|---|---|
| Date | 2014-11-18 15:49 -0800 |
| Message-ID | <234d9da7-2355-4719-9661-cf6e45cbb36a@googlegroups.com> |
| In reply to | #34500 |
On Tuesday, November 18, 2014 4:17:06 PM UTC-5, Rod Pemberton wrote: > > Did anyone here _actually_ read the linked to overview > of the RISC-V instruction set they're using? I did. > "Optional variable-length instructions to both expand > available instruction encoding space and to support an > optional dense instruction encoding for improved > performance, static code size, and energy efficiency." > > http://riscv.org/ > > So, that's VLIW and CISC *plus* RISC, all in one package. > I can't see how that's much different from modern x86, if any. > As an open design, the very first thing it's going to get is > an open, standardized set of CISC instructions ... You can > pretty much guarantee that due to human nature. This is the maximum it is designed for. It all depends on the implementation. I am sure a description like this is available for the ARM family, too. But this doesn't mean that each ARM micro has it all. > Now, it seems, we have a RISC pioneer supporting both CISC > and VLIW. Amazing! I'd say he _clearly_ *missed* something. > Maybe, he missed having some CISC instructions during his > first time around with RISC. We will see when there is a result. Evaluation or simulation is possible with the ZedBoard or the Zybo board containing Xilinx Zynq chips and an ARM processor.
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| From | the_gavino_himself <visphatesjava@gmail.com> |
|---|---|
| Date | 2014-11-23 19:45 -0800 |
| Message-ID | <def06a2b-d306-4c30-9338-cbb3d98d3480@googlegroups.com> |
| In reply to | #34500 |
On Tuesday, November 18, 2014 4:17:06 PM UTC-5, Rod Pemberton wrote: > On Tue, 18 Nov 2014 05:56:39 -0500, Andrew Haley > <andrew29@littlepinkcloud.invalid> wrote: > > visualforth@rocketmail.com wrote: > >> On Monday, November 17, 2014 5:26:05 AM UTC-5, JUERGEN wrote: > > >>> Is anybody here involved in their project, to make them aware of > >>> requirements to run Forth efficiently? > >>> > >> One argument is "Popular commercial ISAs are complex. The dominant > >> commercial ISAs (x86 and ARM) are both very complex to implement in > >> hardware to the level of supporting common software stacks and > >> operating systems. Worse, nearly all the complexity is due to bad, > >> or at least outdated, ISA design decisions rather than features that > >> truly improve efficiency." > >> > >> Seems to be they skipped the chapter of stack machines in McClusky's > >> "Design of Digital Computers". > > > > One of the architects is David Patterson -- who actually invented the > > term RISC -- so I think that idea that anyone "skipped the chapter" is > > ridiculous. > > > > Did anyone here _actually_ read the linked to overview > of the RISC-V instruction set they're using? > > "Optional variable-length instructions to both expand > available instruction encoding space and to support an > optional dense instruction encoding for improved > performance, static code size, and energy efficiency." > > http://riscv.org/ > > So, that's VLIW and CISC *plus* RISC, all in one package. > I can't see how that's much different from modern x86, if any. > As an open design, the very first thing it's going to get is > an open, standardized set of CISC instructions ... You can > pretty much guarantee that due to human nature. > > Now, it seems, we have a RISC pioneer supporting both CISC > and VLIW. Amazing! I'd say he _clearly_ *missed* something. > Maybe, he missed having some CISC instructions during his > first time around with RISC. > > LOL. > > As people look for new solutions to old problems, they > inevitably recycle old solutions and call them new. > First, it was the MILL architecture, now it's lowRISC. > What's next? A 1024-bit PDP-11? A 1Thz 6502? Z80E9? > > > Rod Pemberton What new cpu would you promote?
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| From | rickman <gnuarm@gmail.com> |
|---|---|
| Date | 2014-11-23 23:45 -0500 |
| Message-ID | <m4ud5i$3it$1@dont-email.me> |
| In reply to | #34590 |
On 11/23/2014 10:45 PM, the_gavino_himself wrote: > On Tuesday, November 18, 2014 4:17:06 PM UTC-5, Rod Pemberton wrote: >> On Tue, 18 Nov 2014 05:56:39 -0500, Andrew Haley >> <andrew29@littlepinkcloud.invalid> wrote: >>> visualforth@rocketmail.com wrote: >>>> On Monday, November 17, 2014 5:26:05 AM UTC-5, JUERGEN wrote: >> >>>>> Is anybody here involved in their project, to make them aware of >>>>> requirements to run Forth efficiently? >>>>> >>>> One argument is "Popular commercial ISAs are complex. The dominant >>>> commercial ISAs (x86 and ARM) are both very complex to implement in >>>> hardware to the level of supporting common software stacks and >>>> operating systems. Worse, nearly all the complexity is due to bad, >>>> or at least outdated, ISA design decisions rather than features that >>>> truly improve efficiency." >>>> >>>> Seems to be they skipped the chapter of stack machines in McClusky's >>>> "Design of Digital Computers". >>> >>> One of the architects is David Patterson -- who actually invented the >>> term RISC -- so I think that idea that anyone "skipped the chapter" is >>> ridiculous. >>> >> >> Did anyone here _actually_ read the linked to overview >> of the RISC-V instruction set they're using? >> >> "Optional variable-length instructions to both expand >> available instruction encoding space and to support an >> optional dense instruction encoding for improved >> performance, static code size, and energy efficiency." >> >> http://riscv.org/ >> >> So, that's VLIW and CISC *plus* RISC, all in one package. >> I can't see how that's much different from modern x86, if any. >> As an open design, the very first thing it's going to get is >> an open, standardized set of CISC instructions ... You can >> pretty much guarantee that due to human nature. >> >> Now, it seems, we have a RISC pioneer supporting both CISC >> and VLIW. Amazing! I'd say he _clearly_ *missed* something. >> Maybe, he missed having some CISC instructions during his >> first time around with RISC. >> >> LOL. >> >> As people look for new solutions to old problems, they >> inevitably recycle old solutions and call them new. >> First, it was the MILL architecture, now it's lowRISC. >> What's next? A 1024-bit PDP-11? A 1Thz 6502? Z80E9? >> >> >> Rod Pemberton > > What new cpu would you promote? Not sure why Rod claims anyone is calling the lowRISC a "new" idea other than the license. I don't think there is much difference in the technical aspects in any of the modern CPUs (other than the x86) that makes one inherently better than another. First there are too many different applications. So what is good for one is poor for another. Even for a specific application a lot depends on the tools to optimize for that processor. Finally, none of it amounts to a hill of beans if no one else uses it and the market has poor demand... tools don't get updated, support falls by the wayside and there ends up not even being many other users to help advance it all. What is new about the lowRISC CPU is the licensing. But whether that will be enough remains to be seen. One thing I can tell you is that it is too large a processor to get much use in FPGAs. It would take a sizable hunk of an FPGA just to hold it. -- Rick
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| From | "Rod Pemberton" <buzzoff@nonamewhichexists.cmm> |
|---|---|
| Date | 2014-11-24 17:18 -0500 |
| Message-ID | <op.xpun87samk81un@localhost> |
| In reply to | #34590 |
On Sun, 23 Nov 2014 22:45:05 -0500, the_gavino_himself <visphatesjava@gmail.com> wrote: > On Tuesday, November 18, 2014 4:17:06 PM UTC-5, Rod Pemberton wrote: >> As people look for new solutions to old problems, they >> inevitably recycle old solutions and call them new. >> First, it was the MILL architecture, now it's lowRISC. >> What's next? A 1024-bit PDP-11? A 1Thz 6502? Z80E9? >> > > What new cpu would you promote? New? None. The physical hardware that a processor must interface with hasn't changed any in decades or multiple decades. The memory interface and method to access devices is the same as the 1970's. Until the needs of the hardware changes radically, to the point of being incompatible with existing designs, the needs of the processor to connect to the hardware will remain fixed, as it is today. I.e., the design of a processor has reached a limit or constraint due to the machine architecture. Rod Pemberton
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| From | anton@mips.complang.tuwien.ac.at (Anton Ertl) |
|---|---|
| Date | 2014-11-23 14:04 +0000 |
| Message-ID | <2014Nov23.150448@mips.complang.tuwien.ac.at> |
| In reply to | #34481 |
Andrew Haley <andrew29@littlepinkcloud.invalid> writes:
>visualforth@rocketmail.com wrote:
>> Source: http://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-54.pdf
...
>It looks like quite a good design, in general: very conservative and
>only uses well-tried principles. I very much like the lack of
>condition codes. I don't like the load and store instructions, which
>seem to be missing some addressing modes you need to generate decent
>code: it seems there is only base+offset addressing.
Works nicely for MIPS and Alpha. Code was decent enough, and also
efficient.
With the results of comparison instructions in general-purpose
registers, this isntruction set seems to be quite in line with these
two ISAs. The instruction names SLT, SLTU, JAL and JALR are the same
as in MIPS and are probably designed to make MIPS programmers feel
familiar; one difference from MIPS is that the MIPS ADD/ADDI
instruction (trap on overflow) is not present, and that the RISC-V
ADD/ADDI instruction corresponds to the MIPS ADDU/ADDIU instruction
(modulo arithmetic).
- anton
--
M. Anton Ertl http://www.complang.tuwien.ac.at/anton/home.html
comp.lang.forth FAQs: http://www.complang.tuwien.ac.at/forth/faq/toc.html
New standard: http://www.forth200x.org/forth200x.html
EuroForth 2014: http://www.euroforth.org/ef14/
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| From | Andrew Haley <andrew29@littlepinkcloud.invalid> |
|---|---|
| Date | 2014-11-23 11:25 -0600 |
| Message-ID | <p_2dneuGE5Afhe_JnZ2dnUU7-N2dnZ2d@supernews.com> |
| In reply to | #34576 |
Anton Ertl <anton@mips.complang.tuwien.ac.at> wrote: > Andrew Haley <andrew29@littlepinkcloud.invalid> writes: >>visualforth@rocketmail.com wrote: >>> Source: http://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-54.pdf > ... >>It looks like quite a good design, in general: very conservative and >>only uses well-tried principles. I very much like the lack of >>condition codes. I don't like the load and store instructions, which >>seem to be missing some addressing modes you need to generate decent >>code: it seems there is only base+offset addressing. > > Works nicely for MIPS and Alpha. Code was decent enough, and also > efficient. I suppose you could argue that the instruction count doesn't matter as long as you have superscalar execution and register renaming, but code density suffers along with the icache hit rate. The highest priority for MIPS was simple a simple and fast decoder and everything else could go hang, but that was a decision based on 1980s constraints. I'm rather surprised to see anyone doing it in 2014. > With the results of comparison instructions in general-purpose > registers, this isntruction set seems to be quite in line with these > two ISAs. Indeed it is. Andrew.
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| From | anton@mips.complang.tuwien.ac.at (Anton Ertl) |
|---|---|
| Date | 2014-11-24 09:36 +0000 |
| Message-ID | <2014Nov24.103647@mips.complang.tuwien.ac.at> |
| In reply to | #34581 |
Andrew Haley <andrew29@littlepinkcloud.invalid> writes:
>Anton Ertl <anton@mips.complang.tuwien.ac.at> wrote:
>> Andrew Haley <andrew29@littlepinkcloud.invalid> writes:
>>>visualforth@rocketmail.com wrote:
>>>> Source: http://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-54.pdf
>> ...
>>>It looks like quite a good design, in general: very conservative and
>>>only uses well-tried principles. I very much like the lack of
>>>condition codes. I don't like the load and store instructions, which
>>>seem to be missing some addressing modes you need to generate decent
>>>code: it seems there is only base+offset addressing.
>>
>> Works nicely for MIPS and Alpha. Code was decent enough, and also
>> efficient.
>
>I suppose you could argue that the instruction count doesn't matter as
>long as you have superscalar execution and register renaming, but code
>density suffers along with the icache hit rate. The highest priority
>for MIPS was simple a simple and fast decoder and everything else
>could go hang, but that was a decision based on 1980s constraints.
And Alpha, which was released in 1992, followed that (and IA-64 did
not even have that). Both Alpha and MIPS have a number of instruction
set extensions, but they never added more addressing modes.
Apparently the Alpha and MIPS architects do not think that additional
addressing modes are needed.
Concerning code size, the compiler and/or stuff like the decision to
enforce position-independent code have a bigger influence than the
instruction set. Here is some data from an old posting:
|Here's some data on code size of Gforth-0.5.0 on various systems
|("text" size reported by size; for HP/UX text size-$LIT$ size):
|
| engine-fast.o main-fast.o gcc version
|386 Linux libc5 21184 6523 2.95.1
|386 Linux libc6 21441 8764 2.7.2.3
|386 Linux libc6.1 16744 9214 2.95.2 --enable-force-reg
|SPARC SunOS4 18976 7640 2.5.8
|SPARC Solaris 20560 9446 2.8.1
|MIPS Ultrix 19552 5088 2.4.5
|MIPS Irix6.2 25124 8652 2.95
|Alpha DU 24464 9568 2.95.1
|Alpha Linux 22624 11968 egcs-1.0.3
|HPPA HP/UX 14952 8048 2.95.2
|PowerPC Linux 19168 10204 2.95.2
Note that for main-fast.o MIPS Ultrix has the smalles text (i.e.,
code) size. So the instruction set obviously does not prevent dense
code. For engine-fast.o MIPS IRIX6.2 has the largest text size, so
the MIPS instruction set does not guarantee small code, either.
>I'm rather surprised to see anyone doing it in 2014.
The MIPS people are doing it in 2014 as well.
- anton
--
M. Anton Ertl http://www.complang.tuwien.ac.at/anton/home.html
comp.lang.forth FAQs: http://www.complang.tuwien.ac.at/forth/faq/toc.html
New standard: http://www.forth200x.org/forth200x.html
EuroForth 2014: http://www.euroforth.org/ef14/
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| From | Andrew Haley <andrew29@littlepinkcloud.invalid> |
|---|---|
| Date | 2014-11-24 06:02 -0600 |
| Message-ID | <X62dna_23tjGg-7JnZ2dnUU7-QGdnZ2d@supernews.com> |
| In reply to | #34594 |
Anton Ertl <anton@mips.complang.tuwien.ac.at> wrote:
> Andrew Haley <andrew29@littlepinkcloud.invalid> writes:
>>Anton Ertl <anton@mips.complang.tuwien.ac.at> wrote:
>>> Andrew Haley <andrew29@littlepinkcloud.invalid> writes:
>>>>visualforth@rocketmail.com wrote:
>>>>> Source: http://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-54.pdf
>>> ...
>>>>It looks like quite a good design, in general: very conservative and
>>>>only uses well-tried principles. I very much like the lack of
>>>>condition codes. I don't like the load and store instructions, which
>>>>seem to be missing some addressing modes you need to generate decent
>>>>code: it seems there is only base+offset addressing.
>>>
>>> Works nicely for MIPS and Alpha. Code was decent enough, and also
>>> efficient.
>>
>>I suppose you could argue that the instruction count doesn't matter as
>>long as you have superscalar execution and register renaming, but code
>>density suffers along with the icache hit rate. The highest priority
>>for MIPS was simple a simple and fast decoder and everything else
>>could go hang, but that was a decision based on 1980s constraints.
>
> And Alpha, which was released in 1992, followed that (and IA-64 did
> not even have that).
Indeed it didn't. But IA-64 was so odd in so many ways that we don't
have to dwell on it.
> Both Alpha and MIPS have a number of instruction set extensions, but
> they never added more addressing modes. Apparently the Alpha and
> MIPS architects do not think that additional addressing modes are
> needed.
I am sure you're right about that.
> Concerning code size, the compiler and/or stuff like the decision to
> enforce position-independent code have a bigger influence than the
> instruction set.
Of course.
> Here is some data from an old posting:
>
> |Here's some data on code size of Gforth-0.5.0 on various systems
> |("text" size reported by size; for HP/UX text size-$LIT$ size):
> |
> | engine-fast.o main-fast.o gcc version
> |386 Linux libc5 21184 6523 2.95.1
> |386 Linux libc6 21441 8764 2.7.2.3
> |386 Linux libc6.1 16744 9214 2.95.2 --enable-force-reg
> |SPARC SunOS4 18976 7640 2.5.8
> |SPARC Solaris 20560 9446 2.8.1
> |MIPS Ultrix 19552 5088 2.4.5
> |MIPS Irix6.2 25124 8652 2.95
> |Alpha DU 24464 9568 2.95.1
> |Alpha Linux 22624 11968 egcs-1.0.3
> |HPPA HP/UX 14952 8048 2.95.2
> |PowerPC Linux 19168 10204 2.95.2
>
> Note that for main-fast.o MIPS Ultrix has the smalles text (i.e.,
> code) size. So the instruction set obviously does not prevent dense
> code.
I don't think this follows at all. You'd have to get some much
clearer information to determine such a thing. In order to determine
the effect of ISA on code size you have to eliminate the compiler as
one of the variables, and that is very hard to do. There's a short
paper at
http://web.eece.maine.edu/~vweaver/papers/iccd09/iccd09_density.pdf
>>I'm rather surprised to see anyone doing it in 2014.
>
> The MIPS people are doing it in 2014 as well.
By "it" I meant "designing a new architcecture with this feature".
Thankfully, AArch64 mostly gets this stuff right.
Andrew.
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| From | anton@mips.complang.tuwien.ac.at (Anton Ertl) |
|---|---|
| Date | 2014-11-24 13:04 +0000 |
| Message-ID | <2014Nov24.140405@mips.complang.tuwien.ac.at> |
| In reply to | #34598 |
Andrew Haley <andrew29@littlepinkcloud.invalid> writes:
>Anton Ertl <anton@mips.complang.tuwien.ac.at> wrote:
>> Here is some data from an old posting:
>>
>> |Here's some data on code size of Gforth-0.5.0 on various systems
>> |("text" size reported by size; for HP/UX text size-$LIT$ size):
>> |
>> | engine-fast.o main-fast.o gcc version
>> |386 Linux libc5 21184 6523 2.95.1
>> |386 Linux libc6 21441 8764 2.7.2.3
>> |386 Linux libc6.1 16744 9214 2.95.2 --enable-force-reg
>> |SPARC SunOS4 18976 7640 2.5.8
>> |SPARC Solaris 20560 9446 2.8.1
>> |MIPS Ultrix 19552 5088 2.4.5
>> |MIPS Irix6.2 25124 8652 2.95
>> |Alpha DU 24464 9568 2.95.1
>> |Alpha Linux 22624 11968 egcs-1.0.3
>> |HPPA HP/UX 14952 8048 2.95.2
>> |PowerPC Linux 19168 10204 2.95.2
>>
>> Note that for main-fast.o MIPS Ultrix has the smalles text (i.e.,
>> code) size. So the instruction set obviously does not prevent dense
>> code.
>
>I don't think this follows at all. You'd have to get some much
>clearer information to determine such a thing. In order to determine
>the effect of ISA on code size you have to eliminate the compiler as
>one of the variables, and that is very hard to do.
If code size is as important as you claim, all compilers would strive
for low code size, and we would not need to eliminate compilers as a
variable. In particular, it would not be the case that the oldest
compiler gives a smaller code size than a newer compiler on the same
architecture.
Given that he compiler plays a role, it seems that the authors of gcc
(between 2.4.5 and 2.95.2) did not think code size as important as you
do.
>There's a short
>paper at
>http://web.eece.maine.edu/~vweaver/papers/iccd09/iccd09_density.pdf
Interestingly, the architectural features the authors look into do not
include differences in available addressing modes. Apparently the
authors did not think that this difference is important.
>>>I'm rather surprised to see anyone doing it in 2014.
>>
>> The MIPS people are doing it in 2014 as well.
>
>By "it" I meant "designing a new architcecture with this feature".
Every time they design a new MIPS processor (and they released some in
2014), they have the opportunity to add new new addressing modes.
There is not as much difference between "new" and "old" architectures
as you seem to believe. The MIPS people have not done so yet, and
neither have the RISC-V people.
>Thankfully, AArch64 mostly gets this stuff right.
Aren't you under NDA or something? This architecture still is not
publically available, so you probably are not allowed to talk about
it. In any case, I will not comment on claims that cannot be veryfied
by me.
- anton
--
M. Anton Ertl http://www.complang.tuwien.ac.at/anton/home.html
comp.lang.forth FAQs: http://www.complang.tuwien.ac.at/forth/faq/toc.html
New standard: http://www.forth200x.org/forth200x.html
EuroForth 2014: http://www.euroforth.org/ef14/
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| From | Bernd Paysan <bernd.paysan@gmx.de> |
|---|---|
| Date | 2014-11-24 14:50 +0100 |
| Message-ID | <m4vd30$b1n$1@dont-email.me> |
| In reply to | #34601 |
Anton Ertl wrote: >>Thankfully, AArch64 mostly gets this stuff right. > > Aren't you under NDA or something? This architecture still is not > publically available, so you probably are not allowed to talk about > it. In any case, I will not comment on claims that cannot be veryfied > by me. There's a GCC released for it. And there's an ISA reference manual, published from ARM: https://www.element14.com/community/servlet/JiveServlet/previewBody/41836-102-1-229511/ARM.Reference_Manual.pdf You can buy an iPhone, iPad or Nexus 9 with that architecture; several Samsung devices have an ARM64 core inside, though it's still used in 32 bit mode (maybe pending Samsung's Android Lollipop release). ARM64 is really a well thought through ISA. It has a lot of useful instructions; for Forth flags, e.g. it has CSETM (conditional set mask), which sets a register either to 0 or -1. The only thing missing for Forth are instructions corresponding to um/mod, sm/rem and fm/mod. Division is 32/32 or 64/64, and either unsigned or symmetric. -- Bernd Paysan "If you want it done right, you have to do it yourself" http://bernd-paysan.de/
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