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gforth 32bit cross compile

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  gforth 32bit cross compile Mark <sv8194@gmail.com> - 2014-12-22 20:32 -0800
    Re: gforth 32bit cross compile Jan Coombs <Jan-54 <jenfhaomndgfwutc@murmic.plus.com>> - 2014-12-25 13:18 +0000
      Re: gforth 32bit cross compile Mark <sv8194@gmail.com> - 2014-12-25 12:19 -0800
        Re: gforth 32bit cross compile Jan Coombs <Jan-54 <jenfhaomndgfwutc@murmic.plus.com>> - 2015-01-05 16:59 +0000
          Re: gforth 32bit cross compile Mark <sv8194@gmail.com> - 2015-01-06 09:26 -0800

#35124 — gforth 32bit cross compile

Hi All,

I tried James Bowman's J1 Forth CPU on an Altera board I have and it works great. But the Altera Nios CPU has a 32bits data bus. How does one compile the following Forth into 32bit CPU machine code:

h# 00000001 h# 00000002 + 

In Jame's cross compiler, a literal is identified by the bit15 of the instruction word read(bit15=1 => a literal). In James's cross compiler, the above machine code would be(hex):

8001
8002
6203

For 32bit, I think it should be:
80000001
80000002
6203

Here I would like to have only 32bit literals but keep instructions as 16bit(e.g., hex 6203 -> ALU/+). Of course, all the ALU operations are done in 32bit, as well as ! @, etc. 

Any help and pointers are appreciated,

Mark

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#35232

On Mon, 22 Dec 2014 20:32:56 -0800 (PST)
Mark <sv8194@gmail.com> wrote:

> Hi All,
> 
> I tried James Bowman's J1 Forth CPU on an Altera board I have and it works great. But the Altera Nios CPU has a 32bits data bus. How does one compile the following Forth into 32bit CPU machine code:
> 
> h# 00000001 h# 00000002 + 

using j1 processor unmodified:

 h# 0001 s>d  h# 0002 s>d  d+ 
or 
 h# 0001 h# 0000  h# 0002  h# 0000  d+   (I think)

Note: d+ is not a primitive because the j1 is a 16b processor. 


If you would like to modify the processor to 32b, then I have 
an executable model of it which shortens the edit-test cycle. 
The model can then export VHDL or Verilog for synthesis. [1]


> In Jame's cross compiler, a literal is identified by the bit15 of the instruction word read(bit15=1 => a literal). In James's cross compiler, the above machine code would be(hex):
> 
> 8001
> 8002
> 6203
> 
> For 32bit, I think it should be:
> 80000001
> 80000002
> 6203
> 
> Here I would like to have only 32bit literals but keep instructions as 16bit(e.g., hex 6203 -> ALU/+). Of course, all the ALU operations are done in 32bit, as well as ! @, etc. 

This is not trivial, and will depend on how you choose to modify the j1 instruction set and data path size.  If large constants use is infrequent it might be better to use multiple instructions for them. [2][3]
> 
> Any help and pointers are appreciated,

Why do you want 32b numbers?  There might be a better way. 
Are you only looking at the Novix style stack processor [4], or would you consider types? 

Jan Coombs. 
-- 
email valid, else fix dots and hyphen
jan4clf2014@murrayhyphenmicroftdotcodotuk

[1] http://myhdl.org/
[2] http://www.microcore.org/Introduction/#instructionarch
[3] http://opencores.org/project,zpu
[4] http://users.ece.cmu.edu/~koopman/stack_computers/sec4_4.html

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#35246

On Thursday, December 25, 2014 5:18:14 AM UTC-8, Jan Coombs <Jan-54 > wrote:
> On Mon, 22 Dec 2014 20:32:56 -0800 (PST)
> Mark <sv...@gmail.com> wrote:
> 
> > Hi All,
> > 
> > I tried James Bowman's J1 Forth CPU on an Altera board I have and it works great. But the Altera Nios CPU has a 32bits data bus. How does one compile the following Forth into 32bit CPU machine code:
> > 
> > h# 00000001 h# 00000002 + 
> 
> using j1 processor unmodified:
> 
>  h# 0001 s>d  h# 0002 s>d  d+ 
> or 
>  h# 0001 h# 0000  h# 0002  h# 0000  d+   (I think)
> 
> Note: d+ is not a primitive because the j1 is a 16b processor. 
> 
> 
> If you would like to modify the processor to 32b, then I have 
> an executable model of it which shortens the edit-test cycle. 
> The model can then export VHDL or Verilog for synthesis. [1]

Nice to see we both speak VHDL/Verilog :-). Forth is very cool in the way that in a Modelsim simulation, it just reads in the assembler code and does exactly what a CPU does and it's 10x faster than loading it to an FPGA then watch the signals with, e.g., Altera's SignalTap. You can see the 2 stacks and ALU operations and everything else clearly in the simulation.

Yes, we could make 32bit operations work on top of the 16bit J1, but it would take extra time and software changes. In the example above, we need to worry about the sign too(J1 takes an extra cycle to "load" a negative number).

I have a hardware background so I don't see much trouble changing the Verilog code to work with 32bits. But I have to confess my software skill is so so.

> > In Jame's cross compiler, a literal is identified by the bit15 of the instruction word read(bit15=1 => a literal). In James's cross compiler, the above machine code would be(hex):
> > 
> > 8001
> > 8002
> > 6203
> > 
> > For 32bit, I think it should be:
> > 80000001
> > 80000002
> > 6203
> > 
> > Here I would like to have only 32bit literals but keep instructions as 16bit(e.g., hex 6203 -> ALU/+). Of course, all the ALU operations are done in 32bit, as well as ! @, etc. 
> 
> This is not trivial, and will depend on how you choose to modify the j1 instruction set and data path size.  If large constants use is infrequent it might be better to use multiple instructions for them. [2][3]

Unfortunately, all the numbers need to be 32bits since I plan to offload the Nios II CPU. I can put 8 J1 CPUs there easily.

> > Any help and pointers are appreciated,
> 
> Why do you want 32b numbers?  There might be a better way. 
> Are you only looking at the Novix style stack processor [4], or would you consider types? 

All the embedded projects I worked on here in the Silicon Valley(San Jose, CA) require a 32bit data bus. It would be better to use a 32bit Forth CPU because its dynamic range. But my boss isn't a fan of Forth so I am trying to do some research when I have some spare time.

I will study the references you listed below.

> Jan Coombs. 
> -- 
> email valid, else fix dots and hyphen
> jan4clf2014@murrayhyphenmicroftdotcodotuk
> 
> [1] http://myhdl.org/
> [2] http://www.microcore.org/Introduction/#instructionarch
> [3] http://opencores.org/project,zpu
> [4] http://users.ece.cmu.edu/~koopman/stack_computers/sec4_4.html

Thanks for your help,
Mark

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#35482

On Thu, 25 Dec 2014 12:19:06 -0800 (PST)
Mark <sv8194@gmail.com> wrote:

> Nice to see we both speak VHDL/Verilog :-).  

Well..., I've used VHDL for modelling, and read quite a bit of Verilog, but I use MyHDL for design and modelling [1], and this exports code in the other 'proper' languages for synthesis, which I rarely look at.  MyHDL, like Forth, provides a quick, edit & test cycle, using just a single tool environment.  

> I have a hardware background so I don't see much trouble changing the Verilog code to work with 32bits. But I have to confess my software skill is so so. 

If you are not well experienced in the software side, then choosing a well-proven design that fits your requirements would be lowest risk. Klaus Schleseik's might be good [2], there was also a SOD32. 

 
> I will study the references you listed below.

I hope they are proving useful. 
 
> > 
> > [1] http://myhdl.org/
> > [2] http://www.microcore.org/Introduction/#instructionarch
> > [4] http://users.ece.cmu.edu/~koopman/stack_computers/sec4_4.html
> 
> Thanks for your help,
> Mark

Welcome, please let us know which route you choose to pursue. 

Jan Coombs
-- 
email valid, else fix dots and hyphen
jan4clf2014@murrayhyphenmicroftdotcodotuk

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#35509

On Monday, January 5, 2015 8:59:57 AM UTC-8, Jan Coombs <Jan-54 > wrote:
> On Thu, 25 Dec 2014 12:19:06 -0800 (PST)
> Mark <sv...@gmail.com> wrote:
> 
> > Nice to see we both speak VHDL/Verilog :-).  
> 
> Well..., I've used VHDL for modelling, and read quite a bit of Verilog, but I use MyHDL for design and modelling [1], and this exports code in the other 'proper' languages for synthesis, which I rarely look at.  MyHDL, like Forth, provides a quick, edit & test cycle, using just a single tool environment.  

myHDL looks cool.

> > I have a hardware background so I don't see much trouble changing the Verilog code to work with 32bits. But I have to confess my software skill is so so. 
> 
> If you are not well experienced in the software side, then choosing a well-proven design that fits your requirements would be lowest risk. Klaus Schleseik's might be good [2], there was also a SOD32. 

Thanks, Jan. SOD32 might be exactly what I am looking for. I am going to study it in detail and its cross compiler. 

> > I will study the references you listed below.
> 
> I hope they are proving useful. 
>  
> > > 
> > > [1] http://myhdl.org/
> > > [2] http://www.microcore.org/Introduction/#instructionarch
> > > [4] http://users.ece.cmu.edu/~koopman/stack_computers/sec4_4.html
> > 
> > Thanks for your help,
> > Mark
> 
> Welcome, please let us know which route you choose to pursue. 

I plan to use J1's 16bit instruction format(32bit literals). There is an unused bit in ALU encoding. I will use it for some special operations(e.g., invalid instruction due to 32bit alignment). I will see if I can use SOD32 to generate the 32bit machine code and optimize instructions such as ";".

> Jan Coombs
> -- 
> email valid, else fix dots and hyphen
> jan4clf2014@murrayhyphenmicroftdotcodotuk

Best,
Mark

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