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Re: Very good news from AMD

Started byMitchAlsup <MitchAlsup@aol.com>
First post2011-07-10 11:11 -0700
Last post2011-07-11 08:37 -0400
Articles 6 — 4 participants

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  Re: Very good news from AMD MitchAlsup <MitchAlsup@aol.com> - 2011-07-10 11:11 -0700
    Re: Very good news from AMD Jason Riedy <jason@lovesgoodfood.com> - 2011-07-10 14:25 -0400
      Re: Very good news from AMD "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-07-10 12:25 -0700
      Re: Very good news from AMD Quadibloc <jsavard@ecn.ab.ca> - 2011-07-10 15:29 -0700
        Re: Very good news from AMD Quadibloc <jsavard@ecn.ab.ca> - 2011-07-10 15:32 -0700
        Re: Very good news from AMD Jason Riedy <jason@lovesgoodfood.com> - 2011-07-11 08:37 -0400

#2456 — Re: Very good news from AMD

FromMitchAlsup <MitchAlsup@aol.com>
Date2011-07-10 11:11 -0700
SubjectRe: Very good news from AMD
Message-ID<251375a3-3e9e-4fa1-a25d-f755f475d378@glegroupsg2000goo.googlegroups.com>
On Sunday, July 10, 2011 1:46:07 AM UTC-5, Andy Krazy Glew wrote:
> Memory may be failing me, but I think that the MTA was a fixed barrel 
> scheduled machine.  Did thy not have a fixed 128 threads per node, and 
> always switch from thread to thread, every cycle, with no variation in 
> the schedule?

The pipeline was a "fixed barrel", however a thread was only "out of contention" for another instruction slot while a current instruction was "not performed". Thus, a single thread could get about 1/8th of the machine performance.

Mitch

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#2458

FromJason Riedy <jason@lovesgoodfood.com>
Date2011-07-10 14:25 -0400
Message-ID<87liw6q9he.fsf@NaN.sparse.dyndns.org>
In reply to#2456
And MitchAlsup writes:
> Thus, a single thread could get about 1/8th of the machine
> performance.

Actually, only one instruction is allowed in the 40-deep pipe at
a time.  So it's 1/40th of 500MHz (XMT, 220MHz MTA2, etc.)...
This machine makes Amdahl giggle, but it can keep all its TiBs of
memory busy.
-- 
Jason

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#2460

From"Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net>
Date2011-07-10 12:25 -0700
Message-ID<4E19FCB0.1060602@SPAM.comp-arch.net>
In reply to#2458
On 7/10/2011 11:25 AM, Jason Riedy wrote:
> And MitchAlsup writes:
>> Thus, a single thread could get about 1/8th of the machine
>> performance.
>
> Actually, only one instruction is allowed in the 40-deep pipe at
> a time.  So it's 1/40th of 500MHz (XMT, 220MHz MTA2, etc.)...
> This machine makes Amdahl giggle, but it can keep all its TiBs of
> memory busy.


The GPUs allow multiple cycles of a vector instruction to be in the pipe 
at the same time.

AMD also says that the current GPUs allow different clauses, as long as 
they are guaranteed independent, to be in the pipe at the same time.

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#2462

FromQuadibloc <jsavard@ecn.ab.ca>
Date2011-07-10 15:29 -0700
Message-ID<b66281c8-6646-4da3-86e6-86f6e30bd62c@g12g2000yqd.googlegroups.com>
In reply to#2458
On Jul 10, 12:25 pm, Jason Riedy <ja...@lovesgoodfood.com> wrote:

> Actually, only one instruction is allowed in the 40-deep pipe at
> a time.

Huh? What would be the point of having a pipeline if it can only
handle one instruction at a time?

The whole point of a pipeline is that every stage in the pipeline can,
in the best case, be executing a different stage of a different
instruction.

Of course, I suppose it is possible for a machine to have a pipeline
optimized for vector instructions that is filled with different stages
of operation on different vector elements, but which can only handle
one vector instruction at a time - and no pipeline for regular
instructions. Is that what you're referring to here?

Seymour Cray tried in his designs to avoid that trap.

John Savard

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#2463

FromQuadibloc <jsavard@ecn.ab.ca>
Date2011-07-10 15:32 -0700
Message-ID<e04ab5af-ae17-4979-b972-c3379b77469e@n5g2000yqh.googlegroups.com>
In reply to#2462
On Jul 10, 4:29 pm, Quadibloc <jsav...@ecn.ab.ca> wrote:

> Of course, I suppose it is possible for a machine to have a pipeline
> optimized for vector instructions that is filled with different stages
> of operation on different vector elements, but which can only handle
> one vector instruction at a time - and no pipeline for regular
> instructions. Is that what you're referring to here?

Oh, this is the new AMD machine you're referring to. Although that
sounds bad, it's an improvement on the GPU design that it is based on,
because that was very limited and specialized. So, yes, it's only good
at working with long vectors, but at least now it can do general
operations on them instead of stereotyped ones specifically related to
graphics.

John Savard

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#2465

FromJason Riedy <jason@lovesgoodfood.com>
Date2011-07-11 08:37 -0400
Message-ID<87vcv9ouwa.fsf@NaN.sparse.dyndns.org>
In reply to#2462
And Quadibloc writes:
>> Actually, only one instruction is allowed in the 40-deep pipe
>> at a time.
>
> Huh? What would be the point of having a pipeline if it can
> only handle one instruction at a time?

One instruction per XMT/MTA hardware stream.  So 40 streams can
be in flight at once out of 128 (MTA) or 100 (XMT) available
hardware streams.  Each stream is independent.  This *should*
allow avoiding interlocks, but...
-- 
Jason

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