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| Message-ID | <4DF3A164.5030504@SPAM.comp-arch.net> (permalink) |
|---|---|
| Date | 2011-06-11 10:09 -0700 |
| From | "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> |
| Organization | comp-arch.net |
| Newsgroups | alt.comp.periphs.videocards.nvidia.programming, comp.arch |
| Subject | Re: Cuda Q1: Multi Stage/Multiple Kernels/Multiple Passes Invokation Performance Penalty ? |
| References | <a47b8$4deff767$5419acc3$30733@cache2.tilbu1.nb.home.nl> |
Cross-posted to 2 groups.
On 6/8/2011 3:27 PM, Skybuck Flying wrote: > My question is the following: > > Suppose the following code is executed: > > Kernel 1 > Kernel 2 > Kernel 3 > Kernel 4 > etc > Kernel 10 > > Is there a performanc penalty for invoking a kernel ? > > If so how much of a performance penalty ? How many cycles do it take for > a kernel to start executing ? You are at the leading edge of GPU capabilities. Just a few years ago, all GPUs (at least, all Nvidia and AMD/ATI) GPUs could only execute one kernel on the GPU at a time. So the kernels could not execute in parallel. If you had one kernel that only occupied a single SIMD engine, all of the other SIMD engines went idle until that kernel finished. If you had a kernel that occupied M*N+1 SIMD engines, where N is the number in your GPU ... you should be able to see the fragmentation. Now, I must admit that I have trouble following the incremental steps here. It seems obvious to me that ultimately we want to have different kernels from different users running on different SIMDs at the same time. But, as far as I can tell, the current state of the art is that * Nvidia allows different kernels from the same task to run simultaneously. But not different kernels from different tasks. * AMD/ATI doesn't alllow this at all at the moment, but is rumoured to be about to leapfrog Nvidia's capability. I expect that I will be corrected by people who know the details. I conjecture that these limitations are in part due to limited memory protexction hardware in the GPUs. GPUs do have TLBs and the like, but details are sparse: I conjecture that they cannot currently handle different user privileges at the same time, that the entire GPU is in only a single security context. Similar problems held supercomputers back for years. I remember that the Transputer Meiko computing surface could not handle two different tasks at the same time.
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Cuda Q1: Multi Stage/Multiple Kernels/Multiple Passes Invokation Performance Penalty ? "Skybuck Flying" <Windows7IsOK@DreamPC2006.com> - 2011-06-09 00:27 +0200
Re: Cuda Q1: Multi Stage/Multiple Kernels/Multiple Passes Invokation Performance Penalty ? "Skybuck Flying" <Windows7IsOK@DreamPC2006.com> - 2011-06-09 00:49 +0200
Re: Cuda Q1: Multi Stage/Multiple Kernels/Multiple Passes Invokation Performance Penalty ? "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-06-11 10:09 -0700
Re: Cuda Q1: Multi Stage/Multiple Kernels/Multiple Passes Invokation Performance Penalty ? "Skybuck Flying" <Windows7IsOK@DreamPC2006.com> - 2011-06-11 23:25 +0200
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