processor core validation

From	al.basili@gmail.com (alb)
Newsgroups	comp.arch.embedded, comp.arch.fpga
Subject	processor core validation
Followup-To	comp.arch.embedded
Date	2015-02-08 22:02 +0000
Message-ID	<cjq4nnFu1psU2@mid.individual.net> (permalink)

Cross-posted to 2 groups.

Followups directed to: comp.arch.embedded

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Hi everyone,

I was wondering if anyone can point me to some formal method to validate 
a soft processor core. 

We have the source code (vhdl) and a simulation environment to load 
programs and execute them, but I'm not sure in this case code coeverage 
will be sufficient. What about cases like interrupt handling?

I can run Dhrystone or CoreMark, but will it be sufficient?

Any idea/pointer/comment is appreciated,

Al

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
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Thread

processor core validation al.basili@gmail.com (alb) - 2015-02-08 22:02 +0000
  Re: processor core validation HT-Lab <hans64@htminuslab.com> - 2015-02-09 09:08 +0000
  Re: processor core validation al.basili@gmail.com (alb) - 2015-02-11 22:12 +0000
  Re: processor core validation "" <93490@FPGARelated> - 2015-03-28 12:11 -0500

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