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Groups > comp.arch.embedded > #28772 > unrolled thread
| Started by | Dave Nadler <drn@nadler.com> |
|---|---|
| First post | 2019-08-26 05:23 -0700 |
| Last post | 2019-08-27 12:38 -0700 |
| Articles | 7 — 4 participants |
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What is TI PRU-ICSS processor core? Dave Nadler <drn@nadler.com> - 2019-08-26 05:23 -0700
Re: What is TI PRU-ICSS processor core? Paul Rubin <no.email@nospam.invalid> - 2019-08-26 13:25 -0700
Re: What is TI PRU-ICSS processor core? Rick C <gnuarm.deletethisbit@gmail.com> - 2019-08-27 00:19 -0700
Re: What is TI PRU-ICSS processor core? Paul Rubin <no.email@nospam.invalid> - 2019-08-27 00:25 -0700
Re: What is TI PRU-ICSS processor core? Rick C <gnuarm.deletethisbit@gmail.com> - 2019-08-27 00:39 -0700
Re: What is TI PRU-ICSS processor core? David Brown <david.brown@hesbynett.no> - 2019-08-27 09:52 +0200
Re: What is TI PRU-ICSS processor core? Dave Nadler <drn@nadler.com> - 2019-08-27 12:38 -0700
| From | Dave Nadler <drn@nadler.com> |
|---|---|
| Date | 2019-08-26 05:23 -0700 |
| Subject | What is TI PRU-ICSS processor core? |
| Message-ID | <0e7b1a2c-7dde-4c94-9d82-32b633417df8@googlegroups.com> |
TI's web page is here, but doesn't explain origin of instruction set? http://processors.wiki.ti.com/index.php/PRU-ICSS Anybody here have experience with these parts, or know where they're used? Thanks, Best Regards, Dave
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| From | Paul Rubin <no.email@nospam.invalid> |
|---|---|
| Date | 2019-08-26 13:25 -0700 |
| Message-ID | <87d0grisir.fsf@nightsong.com> |
| In reply to | #28772 |
Dave Nadler <drn@nadler.com> writes: > TI's web page is here, but doesn't explain origin of instruction set? > http://processors.wiki.ti.com/index.php/PRU-ICSS > Anybody here have experience with these parts, or know where they're used? They are in the Beaglebone SOC among other places. The instruction set presumably originated in some weird legacy part. It is ... idiosyncratic. But there are C and C++ compilers for it now. Web search on "beaglebone pru" finds good info. Maybe start here: https://beagleboard.org/pru
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| From | Rick C <gnuarm.deletethisbit@gmail.com> |
|---|---|
| Date | 2019-08-27 00:19 -0700 |
| Message-ID | <f57327fd-3822-431d-8d2d-1281e0b9bdc5@googlegroups.com> |
| In reply to | #28774 |
On Monday, August 26, 2019 at 4:25:05 PM UTC-4, Paul Rubin wrote: > Dave Nadler <drn@nadler.com> writes: > > TI's web page is here, but doesn't explain origin of instruction set? > > http://processors.wiki.ti.com/index.php/PRU-ICSS > > Anybody here have experience with these parts, or know where they're used? > > They are in the Beaglebone SOC among other places. The instruction set > presumably originated in some weird legacy part. It is ... idiosyncratic. > But there are C and C++ compilers for it now. > > Web search on "beaglebone pru" finds good info. Maybe start here: > > https://beagleboard.org/pru By "legacy" part you mean the first TI ARM that used it? Or did it come from an unrelated design? -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209
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| From | Paul Rubin <no.email@nospam.invalid> |
|---|---|
| Date | 2019-08-27 00:25 -0700 |
| Message-ID | <878srfhxx4.fsf@nightsong.com> |
| In reply to | #28775 |
Rick C <gnuarm.deletethisbit@gmail.com> writes: > By "legacy" part you mean the first TI ARM that used it? Or did it > come from an unrelated design? I don't know its origins but just looking at its instruction set, it seems to come from an earlier era of cpu design than what we usually deal with today. Its heritage may have been in industrial automation rather than computing. It's not my area but I think PLC's originally didn't have the features of normal microprocessors, but gradually acquired them, and now they have normal microprocessors inside.
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| From | Rick C <gnuarm.deletethisbit@gmail.com> |
|---|---|
| Date | 2019-08-27 00:39 -0700 |
| Message-ID | <bd838331-e771-4804-86f0-df0e770cb671@googlegroups.com> |
| In reply to | #28776 |
On Tuesday, August 27, 2019 at 3:26:04 AM UTC-4, Paul Rubin wrote: > Rick C <gnuarm.deletethisbit@gmail.com> writes: > > By "legacy" part you mean the first TI ARM that used it? Or did it > > come from an unrelated design? > > I don't know its origins but just looking at its instruction set, it > seems to come from an earlier era of cpu design than what we usually > deal with today. Its heritage may have been in industrial automation > rather than computing. It's not my area but I think PLC's originally > didn't have the features of normal microprocessors, but gradually > acquired them, and now they have normal microprocessors inside. Maybe the instruction set is optimized for it's application and construction. I haven't looked at it in detail, but I've been told it isn't intended to be general purpose. I'm pretty sure they aren't from PLCs. -- Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209
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| From | David Brown <david.brown@hesbynett.no> |
|---|---|
| Date | 2019-08-27 09:52 +0200 |
| Message-ID | <qk2ng1$12u$1@dont-email.me> |
| In reply to | #28777 |
On 27/08/2019 09:39, Rick C wrote: > On Tuesday, August 27, 2019 at 3:26:04 AM UTC-4, Paul Rubin wrote: >> Rick C <gnuarm.deletethisbit@gmail.com> writes: >>> By "legacy" part you mean the first TI ARM that used it? Or did it >>> come from an unrelated design? >> >> I don't know its origins but just looking at its instruction set, it >> seems to come from an earlier era of cpu design than what we usually >> deal with today. Its heritage may have been in industrial automation >> rather than computing. It's not my area but I think PLC's originally >> didn't have the features of normal microprocessors, but gradually >> acquired them, and now they have normal microprocessors inside. > > Maybe the instruction set is optimized for it's application and construction. I haven't looked at it in detail, but I've been told it isn't intended to be general purpose. > > I'm pretty sure they aren't from PLCs. > I've only had a very quick look at the PRU information on the web, but it doesn't look like a PLC-optimised cpu to me. For PLC work, you expect lots of bit handling instructions to suit the chains of and/or "relays" in typical PLC programming. A targeted cpu is also likely to support things like timers in the instruction set. You'd see BCD as a strong alternative to binary (not just BCD arithmetic instructions, but things like indexed addressing using BCD offsets), and you'd expect a heavy bias towards 16-bit and bit types.
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| From | Dave Nadler <drn@nadler.com> |
|---|---|
| Date | 2019-08-27 12:38 -0700 |
| Message-ID | <d563521e-095c-4fcf-8c72-b89c0438ae25@googlegroups.com> |
| In reply to | #28774 |
On Monday, August 26, 2019 at 4:25:05 PM UTC-4, Paul Rubin wrote: > They are in the Beaglebone SOC among other places. The instruction set > presumably originated in some weird legacy part. It is ... idiosyncratic. > But there are C and C++ compilers for it now. > > Web search on "beaglebone pru" finds good info. Maybe start here: > > https://beagleboard.org/pru Thanks Paul, interesting stuff.
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