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Re: USART interrupt on transmission

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pozz <pozzugno@gmail.com> wrote:
> The UART/USART peripheral usually available in many microcontrollers 
> triggers a few interrupts. Two of them are DRE (data register empty, as 
> named in AVR documentation) and TXC (transmitter complete).
> 
> The first can be used to feed the TX FIFO even during shifting out the 
> last pushed data.
> 
> Documentation usually lacks details on these interrupts, for example 
> exactly WHEN they are triggered.
> I made some tests on SAMD20 (from Atmel/Microchip) and LPC54628 (from 
> NXP) and found a difference.
> 
> When the UART isn't transmitting, the DRE flag is set because it is 
> possible to push some data on TX FIFO that is empty. When you enable DRE 
> interrupt, the relevant ISR is triggered immediately because the flag is 
> already set.
> In the ISR you usually push the first data to write and return.
> The first data is immediately moved to the shift register so the TX FIFO 
> is again empty in a very short time, so the DRE interrupt is triggered 
> again.
> 
> There's a subtle difference between the two MCUs above.
> 
> On SAMD21 the second DRE interrupt is triggered immediately after the 
> first ISR returns.
> 
> On LPC54628 the second DRE interrupt is triggered AFTER a start bit 
> delay. It seems the first outgoing data stays in the TX FIFO during 
> transmission of the start bit and moved out only after that period.
> LPC54628 USART has an hardware TX FIFO, but I'm not using it because I 
> configured the peripheral to trigger DRE interrupt when TX FIFO is empty.
> 
> The behaviour of LPC54628 is interesting. It can be used to enable an 
> external transceiver after a few dummy bytes to have a short delay in 
> replying on the bus, allowing the sender (that could be slower) to 
> change its direction.
> If dummy bytes are 0xFF (that appears on the wire as a start bit only), 
> I can enable the driver in DRE ISR when I'm ready to push the first 
> useful data. In this way, all the dummy bytes will not appear really on 
> the wire.
> 
> On SAMD20 devices this can't be done, because you would enable the 
> driver before the start bit of the last dummy byte, so really 
> transmitting it on the wire.
> You need to disable DRE interrupt in the DRE ISR of the last dummy byte, 
> wait for TXC interrupt to enable the driver and enable again DRE 
> interrupt. Push all useful data in DRE ISR and, at the last, disable 
> again DRE and wait for TXC ISR to change again the direction of the 
> transceiver.

Thanks for interesting info.  However, it is not clear why do
you want to sent dummy bytes?  AFACS all you need is a little
delay and for delay I would use timer.

-- 
                              Waldek Hebisch

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USART interrupt on transmission pozz <pozzugno@gmail.com> - 2022-03-26 09:00 +0100
  Re: USART interrupt on transmission antispam@math.uni.wroc.pl - 2022-03-28 14:57 +0000
    Re: USART interrupt on transmission pozz <pozzugno@gmail.com> - 2022-03-28 17:54 +0200
      Re: USART interrupt on transmission antispam@math.uni.wroc.pl - 2022-03-28 21:44 +0000
        Re: USART interrupt on transmission Andrew Smallshaw <andrews@sdf.org> - 2022-04-22 17:15 +0000

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