Groups > comp.arch.embedded > #20015

processor core validation

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From	al.basili@gmail.com (alb)
Newsgroups	comp.arch.embedded, comp.arch.fpga
Subject	processor core validation
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Date	8 Feb 2015 22:02:31 GMT
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Hi everyone,

I was wondering if anyone can point me to some formal method to validate 
a soft processor core. 

We have the source code (vhdl) and a simulation environment to load 
programs and execute them, but I'm not sure in this case code coeverage 
will be sufficient. What about cases like interrupt handling?

I can run Dhrystone or CoreMark, but will it be sufficient?

Any idea/pointer/comment is appreciated,

Al

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processor core validation al.basili@gmail.com (alb) - 2015-02-08 22:02 +0000
  Re: processor core validation Tim Wescott <tim@seemywebsite.com> - 2015-02-08 18:13 -0600
    Re: processor core validation al.basili@gmail.com (alb) - 2015-02-09 17:03 +0000
      Re: processor core validation Tim Wescott <seemywebsite@myfooter.really> - 2015-02-09 13:37 -0600
        Re: processor core validation al.basili@gmail.com (alb) - 2015-02-11 22:12 +0000
          Re: processor core validation rickman <gnuarm@gmail.com> - 2015-02-11 20:18 -0500
            Re: processor core validation al.basili@gmail.com (alb) - 2015-02-12 08:08 +0000
  Re: processor core validation HT-Lab <hans64@htminuslab.com> - 2015-02-09 09:04 +0000
    Re: processor core validation Paul E Bennett <Paul_E.Bennett@topmail.co.uk> - 2015-02-09 09:41 +0000
      Re: processor core validation HT-Lab <hans64@htminuslab.com> - 2015-02-09 11:35 +0000
      Re: processor core validation Tom Gardner <spamjunk@blueyonder.co.uk> - 2015-02-09 12:19 +0000
    Re: processor core validation al.basili@gmail.com (alb) - 2015-02-09 17:16 +0000

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