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Groups > comp.compilers > #3179
| From | Steve Lewis <lewissa78@gmail.com> |
|---|---|
| Newsgroups | comp.compilers |
| Subject | PALM challenge |
| Date | 2022-10-01 01:24 -0700 |
| Organization | Compilers Central |
| Message-ID | <22-10-001@comp.compilers> (permalink) |
Lots of new CPUs, sure. But let's explore an old CPU: the 1975 PALM. I'm looking for anyone interested to explore the idea. Maybe prove how robust modern tools are at adapting C, by exploring this ancient instruction set. You won't find much about this instruction set. But, we've found an internal IBM documentation about it. We have an emulator for it. And we have an assembler for it. I'm no expert about this process, hence seeking help. From what I understand, the instruction set has 4 tiers of 32 registers. Each tier is an interrupt level. In Level 0, the first register holds the program counter (and the second register is reserved as a branch target for certain branch instructions- other than that, I think the registers are all fair game). There are no Index registers, and no Overflow/Underflow registers (that I'm aware of). There is a special instruction for accessing some Devices (so retaining the option for some inline assembly would good - these may be necessary for keyboard and screen output). In total it is approximately 45 instructions. -Steve [Architecture described here http://computermuseum.informatik.uni-stuttgart.de/dev/ibm_5110/technik/en/ It doesn't look like it would be all that bad as a target for C although the code to handle the stack might be a bit tedious. -John]
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PALM challenge Steve Lewis <lewissa78@gmail.com> - 2022-10-01 01:24 -0700
Re: PALM challenge gah4 <gah4@u.washington.edu> - 2022-10-01 17:09 -0700
Re: PALM challenge Thomas Koenig <tkoenig@netcologne.de> - 2022-10-02 20:13 +0000
Re: PALM challenge gah4 <gah4@u.washington.edu> - 2022-10-03 04:37 -0700
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