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| From | john larkin <jl@glen--canyon.com> |
|---|---|
| Newsgroups | sci.electronics.design, comp.arch.fpga |
| Subject | Re: fast divider? |
| Date | 2026-03-21 10:29 -0700 |
| Organization | A noiseless patient Spider |
| Message-ID | <cqktrkloju2vg3n9famtl0csrsev0s2b60@4ax.com> (permalink) |
| References | <tuudrkd9jpmrkn4a1nna7o662701uevjmk@4ax.com> <189dc18427b8b905$12514$2031059$4006de53@news.newsgroupdirect.com> <6laorktu6oiu397vthkra4ilcdsqdtqpb0@4ax.com> <10plapt$26c7q$6@dont-email.me> <b6ycnSn0YLzjVCP0nZ2dnZfqn_d2XUgE@giganews.com> |
Cross-posted to 2 groups.
On Sat, 21 Mar 2026 09:38:17 -0700, Ross Finlayson <ross.a.finlayson@gmail.com> wrote: >On 03/20/2026 10:36 PM, Bill Sloman wrote: >> On 20/03/2026 4:05 am, john larkin wrote: >>> On Tue, 17 Mar 2026 22:30:01 +0000, someone >>> <cffbf4deb9142bce48974efc0e64dede@example.com> wrote: >>> >>>> I assume these are up-counters, so the thing overflows at all 1's. >>>> Then you only have the one fast carry TPD for the MS18b overflowing >>>> to all 1s when a 1 is clocked into its LSB. One whole clock period >>>> to clock the 1 out of the DFF and meet the setup times for what I >>>> assume is a synchronous LD and its setup for the counters. So that >>>> particular timing criticality is a DFF TPD and a LD setup TSU to >>>> reliably capture the register data. The LD TPD to CLK TSU for the >>>> LS18b counter shouldn't be a problem. This must be very speedy logic >>>> for 150MHz. Do you have a simulator that displays how much margin you >>>> have on this timing, or is it just a bunch waveforms? >>> >>> Yes, loadable up-counter with carry chain. >>> >>> This would be in an FPGA, so the diagram is just a concept. The >>> reality will be VHDL code. And the FPGA boys use the Wishbone >>> architecture and want the counter to be 32 bits, which is OK with me. >>> >>> We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so >>> I expect we could do a divider in that ballpark. The T20 is in the >>> *slow* Efinix family. >>> >>> I think the T20 has 18-bit fast carry chains. >>> >>> After the boys code this, the tools can verify timing. >>> >>> FPGAs are great, but there's a cultural gap between people who draw >>> and people who type. >> >> Can't say I've noticed that, but since I can do both, and most of the >> engineers I've hung out with could too, John Larkin may be projecting here. I base the observation on people that I work with, and lately on hundreds of people that I meet at maker-space meetups. Many are kids with CE/EE degrees who don't know much about electricity and who don't have jobs. A Linked-In ad for fpga coders will get hundreds of applicants in a few days. Circuit designers, not so many. I have a couple of quick tests to find the rare kid that gets electronics. >> > >I have a lot of interest in the Bruchla circuit as about things >like transistor nets to effect things like Fourier-style analysis. > >The Bruchla circuit among accounts of things like integrators >and differentiators, is for the middling account of dividers, >that otherwise doesn't have exactly a simple ideal circuit. > Is there some specific Bruchla frequency divider circuit? There seem to be a lot of 50-year old Bruchla circuits online. Looks like mostly audio. John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics
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fast divider? john larkin <jl@glen--canyon.com> - 2026-03-15 11:47 -0700
Re: fast divider? someone <cffbf4deb9142bce48974efc0e64dede@example.com> - 2026-03-17 22:30 +0000
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-19 10:05 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-21 16:36 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-21 07:52 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-22 03:00 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-27 11:39 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-28 16:44 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-28 14:38 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-29 15:52 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-29 08:18 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-30 16:42 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-30 08:00 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-31 16:35 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-31 02:40 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-31 22:30 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-31 08:14 -0700
Re: fast divider? Buzz McCool <buzz_mccool@yahoo.com> - 2026-03-31 10:41 -0700
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-31 10:57 -0700
Re: fast divider? someone <cffbf4deb9142bce48974efc0e64dede@example.com> - 2026-03-26 23:30 +0000
Re: fast divider? Ross Finlayson <ross.a.finlayson@gmail.com> - 2026-03-21 09:38 -0700
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-21 10:29 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-23 23:49 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-23 08:20 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-24 23:04 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-24 05:56 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-25 02:47 +1100
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