Groups > comp.programming.threads > #1567

Re: Intel SCC 48-core x86 Processor

From	"Chris M. Thomasson" <no@spam.invalid>
Newsgroups	comp.programming.threads, comp.programming
Subject	Re: Intel SCC 48-core x86 Processor
Date	2013-06-19 18:57 -0700
Organization	Aioe.org NNTP Server
Message-ID	<kptnja$pgb$1@speranza.aioe.org> (permalink)
References	<kptfbn$cco$1@dont-email.me> <kptjeo$tkt$1@dont-email.me> <kptk4l$i2f$1@speranza.aioe.org> <51C284DA.4040307@toto.net>

Cross-posted to 2 groups.

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"aminer"  wrote in message news:51C284DA.4040307@toto.net...


> Hello,

> I don't understand something:

> Look at this:

> "wait_for_all_readers_notifications();"

> How can you wait for all the readers ? this algorithm
> do not tell us how to wait for all the readers ?

Yikes! I posted to a brief overall sketch of the algorithm.

Check this for more a more detailed sketch:

https://groups.google.com/forum/?fromgroups#!original/comp.programming.threads/t9O4wI-co8Y/ya3QnzvbajUJ

Sorry about that Aminer.

Anyway, this is one way to do it, e.g., iterate and observe
reader state in writer before the key aspect of asymmetric
memory synchronization actually kicks in...

http://home.comcast.net/~pjbishop/Dave/Asymmetric-Dekker-Synchronization.txt

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Re: Intel SCC 48-core x86 Processor "Chris M. Thomasson" <no@spam.invalid> - 2013-06-19 17:58 -0700
  Re: Intel SCC 48-core x86 Processor "Chris M. Thomasson" <no@spam.invalid> - 2013-06-19 18:57 -0700

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