Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > comp.os.linux.development.system > #191

Re: PCIe Interrupt handling

Show all headers | View raw

new <luvraghu@gmail.com> wrote:
>
>I'm writing driver for pcie xilinx fpga. The fpga hardware team has
>not given me any interrupt status register, interrupt enable register.
>They just said to set the bit 9 in the device control register which
>would enable the interrupt(for read or write completion). Is this
>sufficient to handle the interrupts? When I register the interrupt
>with a shared flag, my handler gets called even when the bit 9 is
>reset, how do i make sure if the appropriate interrupt is being
>received?

If your interrupt is shared, then you have the responsibility to check
whether it was your device that fired the interrupt.  If your device can't
do that, then basically it cannot be used in today's operating systems.

>How do i control it? Do i need to request the fpga hardware
>to add any extra registers?

You need to be able to enable and disable the interrupt, and you need to be
able to answer the question "has our device requested an interrupt?"
Generally, there's also a bit to acknowledge that the last interrupt was
handled.
-- 
Tim Roberts, timr@probo.com
Providenza & Boekelheide, Inc.

Back to comp.os.linux.development.system | Previous | Next — Previous in thread | Next in thread | Find similar

Thread

PCIe Interrupt handling new <luvraghu@gmail.com> - 2011-06-29 04:00 -0700
  Re: PCIe Interrupt handling Tim Roberts <timr@probo.com> - 2011-06-30 01:21 -0700
  Re: PCIe Interrupt handling David Schwartz <davids@webmaster.com> - 2011-07-01 00:46 -0700

csiph-web