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| NNTP-Posting-Date | Sun, 12 Feb 2012 20:35:35 -0600 |
| Message-ID | <4F3876EE.2080104@SPAM.comp-arch.net> (permalink) |
| Date | Sun, 12 Feb 2012 18:35:26 -0800 |
| From | "Andy (Super) Glew" <andy@SPAM.comp-arch.net> |
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| Subject | Re: Trace of CPU Instruction Reordering |
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On 2/12/2012 6:04 PM, Ripunjay Tripathi wrote: > I have studied a few things about instruction re-ordering by > processors and Tomasulo's algorithm. > > In an attempt to understand this topic bit more I want to know if > there is ANY way to (get the trace) see the actual dynamic reordering > done for a given program? > > I want to give an input program and see the "out of order instruction > execution trace" of my program. > > I have access to an IBM-P7 machine and an Intel Core2Duo laptop. Also > please tell me if there is an easy alternative. ftp://download.intel.com/education/highered/research/carmean_slides.pdf gives some examples of pipetrace viewers used at Intel for Pentium 4 (Willamette) circa 2003. (Interesting - the slides have a copyright date circa 2003, but are marked 2005.) By this time such tools were more than 15 years old. I think I remember Glenn Hinton saying that one of the big reasons for the success of P6 was that P6 had good visualization tools. The pipetrace approach was stretched - literally - by Pentium 4, with extremely long pipelines and instruction lifetimes. It became a challenge to see all of the information you wanted on one wide display. (Which is one reason why I am sitting in front of 4 displays right now.)
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Trace of CPU Instruction Reordering Ripunjay Tripathi <ripunjay.tripathi@gmail.com> - 2012-02-12 18:04 -0800 Re: Trace of CPU Instruction Reordering "Andy (Super) Glew" <andy@SPAM.comp-arch.net> - 2012-02-12 18:28 -0800 Re: Trace of CPU Instruction Reordering "Andy (Super) Glew" <andy@SPAM.comp-arch.net> - 2012-02-12 18:35 -0800
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