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Re: The Indexed Instruction Problem Solved!

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Quadibloc wrote:
> 
> On Jul 18, 6:07 pm, MitchAlsup <MitchAl...@aol.com> wrote:
> 
> > Believe it (or not): one customer took serious issue with the Gould (A.K.A S.E.L.) 32/87 executing the NO-OP in the unsed Halfword in zero cycles. They actually wanted the NO-OP executed and take a real execution cycle. For some reason or another this made their Real-time response unpredictable.
> 
> It's a pity you didn't have two possible opcodes for a no-op
> instruction. One could have done that, while another would be an
> ignored space-filler.

Why would you need that?  There wasn't a do-nothing encoding
of a 1-cycle instruction available?  Like mov r0,r0?

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Re: The Indexed Instruction Problem Solved! MitchAlsup <MitchAlsup@aol.com> - 2011-07-18 17:07 -0700
  Gould (was:Re: The Indexed Instruction Problem Solved!) Mike Hore <mike_horeREM@OVE.invalid.aapt.net.au> - 2011-07-19 15:39 +1000
  Re: The Indexed Instruction Problem Solved! nmm1@cam.ac.uk - 2011-07-19 07:14 +0100
    Re: The Indexed Instruction Problem Solved! Terje Mathisen <"terje.mathisen at tmsw.no"> - 2011-07-20 11:26 +0200
  Re: The Indexed Instruction Problem Solved! Quadibloc <jsavard@ecn.ab.ca> - 2011-07-19 01:00 -0700
    Re: The Indexed Instruction Problem Solved! Mark Thorson <nospam@sonic.net> - 2011-07-19 16:54 -0800
      Re: The Indexed Instruction Problem Solved! Quadibloc <jsavard@ecn.ab.ca> - 2011-07-19 18:53 -0700
      Re: The Indexed Instruction Problem Solved! nmm1@cam.ac.uk - 2011-07-20 07:41 +0100
        Re: The Indexed Instruction Problem Solved! Terje Mathisen <"terje.mathisen at tmsw.no"> - 2011-07-20 11:39 +0200

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