Re: CPU design

From	"Carlos E.R." <robin_listas@es.invalid>
Newsgroups	alt.unix.geeks, comp.os.linux.misc
Subject	Re: CPU design
Date	2026-04-04 22:18 +0200
Message-ID	<k988amxcnl.ln2@Telcontar.valinor> (permalink)
References	(12 earlier) <ycGdnYl5Ypeulk30nZ2dnZfqnPcAAAAA@giganews.com> <nri5amx5vr.ln2@Telcontar.valinor> <ycGdnYt5YpeLvk30nZ2dnZfqnPednZ2d@giganews.com> <9o87amxf8l.ln2@Telcontar.valinor> <H_GdnfoN7d6JzEz0nZ2dnZfqnPudnZ2d@giganews.com>

Cross-posted to 2 groups.

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On 2026-04-04 19:57, c186282 wrote:
> On 4/4/26 07:20, Carlos E.R. wrote:
>> On 2026-04-03 22:29, c186282 wrote:
>>> On 4/3/26 16:00, Carlos E.R. wrote:
>>>> On 2026-04-03 20:47, c186282 wrote:
>>>>
>>>> ...
>>>>
>>>>>    Also tried to look up the "how to" for CPU operation.
>>>>>    Endless pages of stuff - but all 'higher level' stuff,
>>>>>    nothing at the base wiring level - explanations rather
>>>>>    than construction schematics.
>>>>
>>>> Because that is another step. Possibly even different people.
>>>
>>>    Didn't find any, even going four or five
>>>    pages in and trying to customize the search
>>>    params a few times.
>>>
>>>    The info is there SOMEWHERE ... but WHERE ???
>>>
>>>    Or do they want you to buy a $150 book ?
>>
>> Possibly. What I learned was in an UNI course, it was not in a book. 
>> In fact, I think they used an imaginary CPU that does not exist, so no 
>> books at all except class notes. I don't remember if there was some 
>> self published book (photocopied).
> 
>    Someone who CAN should put together a simple
>    animation ... show those registers loading
>    at the bit level, the mem fetch, the decode,
>    the data store, what's wired to what with a
>    few-sentence comment for each stage. A 4-bit
>    example would be clearer.
> 
>    Sometime, maybe soon, humans won't know how
>    to do this stuff anymore - it'll all be the
>    AIs ... and then it all becomes 'magic'.
> 
>    Interesting eh ... we only pulled ourselves out
>    of a Magical Universe a few hundred years ago
>    and now we're headed back  :-)
> 
>    What IS the proper sacrifice to the Regional
>    Utility Manager AI ?
> 

I posted a link to an schematic of the 6502, showing all transistors. I 
haven't looked if that guy has created more drawings.

Yes, a simulation would be nice.

Yet I assume that there are university courses teaching how to design a CPU.

-- 
Cheers, Carlos.
ES🇪🇸, EU🇪🇺;

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Re: Mercury "Carlos E.R." <robin_listas@es.invalid> - 2026-04-03 14:33 +0200
  Re: Mercury c186282 <c186282@nnada.net> - 2026-04-03 11:06 -0400
    Re: Mercury Rich <rich@example.invalid> - 2026-04-03 16:51 +0000
      Re: Mercury c186282 <c186282@nnada.net> - 2026-04-03 14:47 -0400
        CPU architecture (was Re: Mercury) John Ames <commodorejohn@gmail.com> - 2026-04-03 12:57 -0700
          Re: CPU architecture (was Re: Mercury) c186282 <c186282@nnada.net> - 2026-04-03 22:45 -0400
            Re: CPU architecture (was Re: Mercury) Rich <rich@example.invalid> - 2026-04-04 03:27 +0000
            Re: CPU architecture (was Re: Mercury) rbowman <bowman@montana.com> - 2026-04-04 04:57 +0000
        CPU design "Carlos E.R." <robin_listas@es.invalid> - 2026-04-03 22:00 +0200
          Re: CPU design c186282 <c186282@nnada.net> - 2026-04-03 16:29 -0400
            Re: CPU design "Carlos E.R." <robin_listas@es.invalid> - 2026-04-04 13:20 +0200
              Re: CPU design c186282 <c186282@nnada.net> - 2026-04-04 13:57 -0400
                Re: CPU design "Carlos E.R." <robin_listas@es.invalid> - 2026-04-04 22:18 +0200
                Re: CPU design Rich <rich@example.invalid> - 2026-04-05 03:44 +0000
                Re: CPU design "Carlos E.R." <robin_listas@es.invalid> - 2026-04-05 13:58 +0200
                Re: CPU design c186282 <c186282@nnada.net> - 2026-04-05 17:19 -0400
                Re: CPU design The Natural Philosopher <tnp@invalid.invalid> - 2026-04-05 12:42 +0100
        Re: Mercury Rich <rich@example.invalid> - 2026-04-03 21:57 +0000
    Re: Mercury rbowman <bowman@montana.com> - 2026-04-03 17:54 +0000
      Re: Mercury c186282 <c186282@nnada.net> - 2026-04-03 22:29 -0400
        Re: Mercury rbowman <bowman@montana.com> - 2026-04-04 04:58 +0000
          Re: Mercury The Natural Philosopher <tnp@invalid.invalid> - 2026-04-04 13:30 +0100
            Re: Mercury c186282 <c186282@nnada.net> - 2026-04-04 13:46 -0400
              Re: Mercury rbowman <bowman@montana.com> - 2026-04-04 19:22 +0000
            Re: Mercury rbowman <bowman@montana.com> - 2026-04-04 19:09 +0000
          Re: Mercury c186282 <c186282@nnada.net> - 2026-04-04 13:50 -0400
    Re: Mercury "Carlos E.R." <robin_listas@es.invalid> - 2026-04-03 21:55 +0200
      Re: Mercury The Natural Philosopher <tnp@invalid.invalid> - 2026-04-04 13:40 +0100
        Re: Mercury Rich <rich@example.invalid> - 2026-04-04 14:32 +0000
          Re: Mercury "Carlos E.R." <robin_listas@es.invalid> - 2026-04-04 18:44 +0200
            Re: Mercury rbowman <bowman@montana.com> - 2026-04-04 19:02 +0000
            Re: Mercury The Natural Philosopher <tnp@invalid.invalid> - 2026-04-05 12:17 +0100
              Re: Mercury "Carlos E.R." <robin_listas@es.invalid> - 2026-04-05 13:59 +0200
                Re: Mercury The Natural Philosopher <tnp@invalid.invalid> - 2026-04-05 13:10 +0100
                Re: Mercury "Carlos E.R." <robin_listas@es.invalid> - 2026-04-05 19:50 +0200
                Re: Mercury rbowman <bowman@montana.com> - 2026-04-05 22:02 +0000
                Re: Mercury Bobbie Sellers <bliss-sf4ever@dslextreme.com> - 2026-04-05 17:01 -0700
                Re: Mercury rbowman <bowman@montana.com> - 2026-04-06 02:05 +0000
                Mandriva was Re: Mercury Bobbie Sellers <bliss-sf4ever@dslextreme.com> - 2026-04-05 21:18 -0700
                Re: Mandriva was Re: Mercury rbowman <bowman@montana.com> - 2026-04-06 16:02 +0000
                Re: Mandriva was Re: Mercury Bobbie Sellers <bliss-sf4ever@dslextreme.com> - 2026-04-06 14:53 -0700
                Re: Mercury The Natural Philosopher <tnp@invalid.invalid> - 2026-04-06 11:01 +0100

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