Re: IBM z196 high word facility

From	Andrew Reilly <areilly---@bigpond.net.au>
Newsgroups	comp.arch
Subject	Re: IBM z196 high word facility
Date	2012-03-05 12:17 +0000
Message-ID	<9rjp60FoucU1@mid.individual.net> (permalink)
References	<4F545B81.4090108@SPAM.comp-arch.net>

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On Sun, 04 Mar 2012 22:21:53 -0800, Andy (Super) Glew wrote:

> So, this is what the [[high-word facility]] does: it provides a limited
> set of instructions that use the upper 32 bit halves of the 64 bit
> registers.

cf. ARM NEON where 5-bit register selectors allowed access to 32 scalar 
32-bit values in an earlier version, but to 32 double precision/64-bit 
SIMD values or 16 128-bit values in later versions.  In these later 
versions only the first 32 elements of the 64-word register set can be 
accessed as 32-bit scalar values.

Not quite the same scheme, but similar motivation, I suspect.  (Also 
lacking the clearly insane bit numbering scheme you mentioned, where the 
"legacy" 32-bit values of the extended registers are called bits 
32-63...  Yes, I prefer little-endian register naming...)

Cheers,

-- 
Andrew

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Thread

IBM z196 high word facility "Andy (Super) Glew" <andy@SPAM.comp-arch.net> - 2012-03-04 22:21 -0800
  Re: IBM z196 high word facility Jean-Marc Bourguet <jm@bourguet.org> - 2012-03-05 11:27 +0100
    Re: IBM z196 high word facility John Levine <johnl@iecc.com> - 2012-03-05 18:07 +0000
  Re: IBM z196 high word facility Andrew Reilly <areilly---@bigpond.net.au> - 2012-03-05 12:17 +0000
  Re: IBM z196 high word facility Quadibloc <jsavard@ecn.ab.ca> - 2012-03-05 09:35 -0800
    Re: IBM z196 high word facility John Levine <johnl@iecc.com> - 2012-03-05 18:09 +0000
      Re: IBM z196 high word facility Quadibloc <jsavard@ecn.ab.ca> - 2012-03-05 12:32 -0800
  Re: IBM z196 high word facility Quadibloc <jsavard@ecn.ab.ca> - 2012-03-22 18:03 -0700

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