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Groups > comp.sys.intel > #135
| Date | 2011-11-02 20:57 -0400 |
|---|---|
| From | Yousuf Khan <bbbl67@spammenot.yahoo.com> |
| Newsgroups | comp.sys.intel |
| Subject | Re: reason for AMD's Bulldozer fiasco? |
| References | <4ea169cc$1@x-privat.org> <4ea20c15$1@news.bnb-lp.com> <6237dab2-f810-42af-a86d-7a43e25c0d41@s11g2000yqi.googlegroups.com> <78udnWh12Z6DjTPTnZ2dnUVZ7sqdnZ2d@giganews.com> <d244b793-dfc9-4f71-a4f8-b552fa8b6a63@u28g2000yqb.googlegroups.com> |
| Message-ID | <4eb1e705$1@news.bnb-lp.com> (permalink) |
| Organization | Send abuse or DMCA complaints to abuse@bnb-lp.com |
On 01/11/2011 4:25 PM, Robert Myers wrote: > The enormously long pipeline wasn't the only distinguishing feature of > NetBurst. According to someone I trust, parts of the NetBurst design > ran at double-time. Thus, parts of the 3GHz processors were already > running at 6GHz, thus explaining in part the enormous power > consumption problem that NetBurst had. Unfortunately, not enough > instructions would run on the faster pipeline to justify the design > strategy, and Intel was caught between an unexpected rock and hard > place. I think you're referring to the P4's floating point unit which was optimized for SSE2, but fell behind in regular x87 floating point. Interestingly, the new AMD Bulldozer floating point unit is expected to perform best in the newer AVX or 256-bit SSE instructions, rather than the older 128-bit SSE instructions. There were other doubled-speed interfaces like their FSB, which was running at 400MHz (eventually became 566MHz, I think), vs. AMD at 200-266MHz, or P3 at 100-133MHz. That required the highest-speed Rambus or DDR memory to make good use of its bus. > The original thought was to get a processor out with a label > frequency in well in excess of 1GHz, leaving AMD in the dust. Known > performance problems would be addressed by beefing up the faster > pipeline. In fact, the needed transistors may well have been in the > original NetBurst design and had to be thrown overboard because of the > power envelope. Intel probably knew a long time ago that the real > problem was power management. They just weren't as fast or as > successful in fixing it as they thought they would be. Which again seems to be the exact same problem that AMD will have to face with Bulldozer. Their next revision stepping is going to be entirely about getting the power consumption under control. I think AMD's biggest problem was not that Bulldozer has low IPC (it does), but that AMD couldn't right away bring Bulldozer out with enough clock frequency to compensate for its IPC. It's now got to really start pushing the clock speeds out. Yousuf Khan
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reason for AMD's Bulldozer fiasco? "Orson Cart" <ex-privat@parts.org> - 2011-10-21 14:47 +0100
Re: reason for AMD's Bulldozer fiasco? Yousuf Khan <bbbl67@spammenot.yahoo.com> - 2011-10-21 20:19 -0400
Re: reason for AMD's Bulldozer fiasco? Robert Myers <rbmyersusa@gmail.com> - 2011-10-30 09:36 -0700
Re: reason for AMD's Bulldozer fiasco? Yousuf Khan <bbbl67@spammenot.yahoo.com> - 2011-10-30 23:03 -0400
Re: reason for AMD's Bulldozer fiasco? Robert Myers <rbmyersusa@gmail.com> - 2011-11-01 13:25 -0700
Re: reason for AMD's Bulldozer fiasco? Yousuf Khan <bbbl67@spammenot.yahoo.com> - 2011-11-02 20:57 -0400
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