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| From | MitchAlsup <MitchAlsup@aol.com> |
|---|---|
| Newsgroups | comp.arch |
| Subject | Re: Ne(ish) IBM z196 synchronization instructions |
| Date | 2012-03-09 08:19 -0800 |
| Organization | http://groups.google.com |
| Message-ID | <15229834.761.1331309987212.JavaMail.geo-discussion-forums@ynbq18> (permalink) |
| References | <4F56E21F.2010903@SPAM.comp-arch.net> <5rnk29-riq.ln1@ntp6.tmsw.no> <1432328.1752.1331156586117.JavaMail.geo-discussion-forums@ynkz21> <4F58E783.2080205@SPAM.comp-arch.net> <2f7n29-nmt.ln1@ntp6.tmsw.no> |
On Thursday, March 8, 2012 11:39:13 AM UTC-6, Terje Mathisen wrote: > Andy (Super) Glew wrote: > > On 3/7/2012 1:43 PM, MitchAlsup wrote: > >> On Wednesday, March 7, 2012 1:00:20 PM UTC-6, Terje Mathisen wrote: > >>> I have some problem figuring out the intended usage for the AND/OR/XOR > >>> versions of this operation: > >> > >> XOR is useful for setting bits and resetting bits (from the same > >> constant). > >> > >> So one can "check in their request" and "checkout their request" using > >> the same value. Otherwise one has to ADD a bit to check in a request > >> and then ADD in the 2's complement to check it back out (or OR on a > >> bit and AND-NOT it back off). > >> > >> Most of the statemachine logic in my simulators uses XOR as in: > >> > >> if( p->state& STATE1 ) > >> p->state ^= STATE1 | STATE2; > >> else > >> > >> // where it is known STATE1 and STATE2 have no common bits > >> // but may have more than one bit set. > >> > >> Mitch > > > > > > Right. But do you need that to be atomic? > > > > Can you have multiple threads using the same p->state at the same time? > > Setting the same bits? > > > > Or possibly setting disjoint bits in the same word? > > > > To get XOR the safely set and clear different bits, you have to know the > > prior state. Perhaps and AND-OR instruction? > > > > AND-OR > > tmp := mem > > tmp &= and_mask (or ~and_mask) > > tmp |= or_mask > > mem := tmp > > > > A nice instruction, but it really wants two immediates. > > > > Exactly, it is hard to figure out a nice usage scenario for the existing > logical versions. I have seen a parallel processing implementation that used the bit to denote which processor was requesting/waiting-for the lock (kernel only). As long as the number of processors is smaller than wordsize this works well. Mitch
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Ne(ish) IBM z196 synchronization instructions "Andy (Super) Glew" <andy@SPAM.comp-arch.net> - 2012-03-06 20:20 -0800
Re: Ne(ish) IBM z196 synchronization instructions "Paul A. Clayton" <paaronclayton@gmail.com> - 2012-03-07 05:43 -0800
Re: Ne(ish) IBM z196 synchronization instructions "Andy (Super) Glew" <andy@SPAM.comp-arch.net> - 2012-03-07 07:00 -0800
Re: Ne(ish) IBM z196 synchronization instructions nmm1@cam.ac.uk - 2012-03-07 15:25 +0000
Re: Ne(ish) IBM z196 synchronization instructions "Paul A. Clayton" <paaronclayton@gmail.com> - 2012-03-09 11:05 -0800
Re: Ne(ish) IBM z196 synchronization instructions Terje Mathisen <"terje.mathisen at tmsw.no"> - 2012-03-07 20:00 +0100
Re: Ne(ish) IBM z196 synchronization instructions MitchAlsup <MitchAlsup@aol.com> - 2012-03-07 13:43 -0800
Re: Ne(ish) IBM z196 synchronization instructions "Andy (Super) Glew" <andy@SPAM.comp-arch.net> - 2012-03-08 09:08 -0800
Re: Ne(ish) IBM z196 synchronization instructions Terje Mathisen <"terje.mathisen at tmsw.no"> - 2012-03-08 18:39 +0100
Re: Ne(ish) IBM z196 synchronization instructions Nomen Nescio <nobody@dizum.com> - 2012-03-08 22:33 +0100
Re: Ne(ish) IBM z196 synchronization instructions "Andy (Super) Glew" <andy@SPAM.comp-arch.net> - 2012-03-08 17:17 -0800
Re: Ne(ish) IBM z196 synchronization instructions MitchAlsup <MitchAlsup@aol.com> - 2012-03-09 08:19 -0800
Re: Ne(ish) IBM z196 synchronization instructions Terje Mathisen <"terje.mathisen at tmsw.no"> - 2012-03-09 17:45 +0100
Re: Ne(ish) IBM z196 synchronization instructions jgk@panix.com (Joe keane) - 2012-03-09 20:30 +0000
Re: Ne(ish) IBM z196 synchronization instructions MitchAlsup <MitchAlsup@aol.com> - 2012-03-09 13:10 -0800
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