Re: TCLE

From	"Edward Rawde" <invalid@invalid.invalid>
Newsgroups	sci.electronics.design
Subject	Re: TCLE
Date	2026-05-05 09:58 -0400
Organization	BWH Usenet Archive (https://usenet.blueworldhosting.com)
Message-ID	<10tct29$qfl$1@nnrp.usenet.blueworldhosting.com> (permalink)
References	(4 earlier) <g9vgvkheh7dhktn6b34d9ivm7p26tusgam@4ax.com> <10tak3o$3r5k7$1@dont-email.me> <fenhvk5d3bqhgjn76i8jb5m66elm8dp96b@4ax.com> <10tc68g$8f2v$1@dont-email.me> <10tcheg$bniu$1@dont-email.me>

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"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:10tcheg$bniu$1@dont-email.me...
> On 5/5/26 09:29, Bill Sloman wrote:
>> On 5/05/2026 5:08 am, john larkin wrote:
>>> On Tue, 5 May 2026 03:13:24 +1000, Bill Sloman <bill.sloman@ieee.org>
>>> wrote:
>>>
>>>> On 4/05/2026 9:19 pm, john larkin wrote:
>>>>> On Mon, 4 May 2026 17:06:00 +1000, Bill Sloman <bill.sloman@ieee.org>
>>>>> wrote:
>>>>>
>>>>>> On 4/05/2026 3:05 am, john larkin wrote:
>>>>>>> On Mon, 4 May 2026 01:19:48 +1000, Bill Sloman <bill.sloman@ieee.org>
>>>>>>> wrote:
>>>>>>>
>>>>>>>> On 4/05/2026 12:09 am, john larkin wrote:
>>>>>>>>> A TCLE, pronounced tickle, is a 3-pin logic element with input A and
>>>>>>>>> outputs X and Y.
>>>>>>>>>
>>>>>>>>> X = A and Y = \A
>>>>>>>>>
>>>>>>>>> with perfect symmetry and zero prop delay. I need several on a very
>>>>>>>>> small board, with 3.3v supply.
>>>>>>>>>
>>>>>>>>> TI once made a TTL part, the 74265, with four inside. Actually,
>>>>>>>>> Digikey will still sell you one. But it's a 5 volt DIP and very slow.
>>>>>>>>>
>>>>>>>>> I could make one from three XOR gates, one to square up the input edge
>>>>>>>>> and two to buffer/invert. Available CMOS quad XORS are slow.
>>>>>>>>>
>>>>>>>>> I could make it from three NC7SV86P5X tiny xors, which would be pretty
>>>>>>>>> fast and symmetric and inelegant.
>>>>>>>>>
>>>>>>>>> A 1 ns tinylogic flipflop would be great but the truth table is wrong.
>>>>>>>>>
>>>>>>>>> What's a boy to do?
>>>>>>>>
>>>>>>>> Grow up?
>>>>>>>>
>>>>>>>> There are LVDS, CML and differential ECL parts which will do what you
>>>>>>>> want - the propagation delay isn't zero but that's an unattainable ideal.
>>>>>>>>
>>>>>>>> https://www.ti.com/lit/wp/snla180/snla180.pdf?ts77795863250&ref_url=https%253A%252F%252Fwww.google.com%252F
>>>>>>>>
>>>>>>>> lists them in general terms. There are parts out there which will run
>>>>>>> >from a 3.3V rail. The voltage swings will small - less than a
>>>>>>> volt, but
>>>>>>>> you are going to be driving terminated transmission lines.
>>>>>>>
>>>>>>> No. I will be driving the high impedance differential input of a pin
>>>>>>> driver thing. It needs at least 3.3v swing on both X and Y.
>>>>>>
>>>>>> Then you need a fast amplifier next to the "pin driver thing".
>>>>>>
>>>>>> Driving large fast voltage swings over distance is a very expensive sport.
>>>>>>
>>>>>>> And my single-ended input is is 3.3v swing from an FPGA, coming in
>>>>>>> over a ribbon cable, pretty much source terminated.
>>>>>>
>>>>>> So you are going to get a reflection at the "pin driver thing" and the
>>>>>> "source termination" in the FPGA driver is not going to be good enough
>>>>>> to prevent some of that being reflected back into the pin driver.
>>>>>
>>>>> Certainly. Source terminating an open-ended transmission line causes a
>>>>> doubling of the wavefront at the hi-z load end and a correspondingly
>>>>> giant reflection back into the driver and works great.
>>>>
>>>> The question is all about the quality of the source termination. The
>>>> driver has it own output impedance and that does tend to vary with
>>>> output voltage.
>>>
>>> We have IBIS simulations of the Trion output drivers, and they look
>>> good. We just bought a 1 GHz Rigol scope and its fet probe, so we'll
>>> be verifying waveforms soon.
>>>
>>> 75 ohms turns out to be a good choice, for ribbon cables and PCBs and
>>> FPGAs.
>>>
>>>>
>>>> "Works great" isn't any kind of quantitative assessment.
>>>
>>> Purchase orders are quantitative.
>>>
>>>
>>>
>>>>
>>>>> The txline will be 75 ohms and the FPGA gives us four choices of drive
>>>>> strength so one should work. A little overshoot at the load end is
>>>>> fine... it overpowers some HF losses.
>>>>
>>>> Varying "drive strength" isn't adjusting the output impedance.In classic
>>>> CMOS the P-channel transistor had a higher output impedance than the
>>>> N-channel parts.
>>>>
>>>> That would lead to under shoot at the positive rail and over-shoot at
>>>> the negative rail.
>>>
>>> A bit of over and undershoot is actually good, for shipping logic
>>> signals around. It speeds up the critical logic threshold transition.
>>>
>>>>
>>>> Presumably the FPGA has four different sizes of transistors, or can
>>>> couple in more devices if you want a higher current output but that
>>>> isn't exactly tuning the output impedance.
>>>>
>>>> In any event you are going to have ripple sloshing back and forth along
>>>> your transmission line, if you can't keep it very short.
>>>>
>>>>>>>> https://www.onsemi.com/download/application-notes/pdf/and8060-d.pdf
>>>>>>>>
>>>>>>>> talks about that.
>>>>>>>>
>>>>>>>> https://www.onsemi.com/download/data-sheet/pdf/mc10lvep11-d.pdf
>>>>>>>>
>>>>>>>> https://www.onsemi.com/download/data-sheet/pdf/mc10lvep16-d.pdf
>>>>>>>>
>>>>>>>> Propagation delays run from 150 to 330psec with a typical 240psec at
>>>>>>>> 25C. Not zero, but quite small.
>>>>>>>
>>>>>>> Yikes. $4.44 each by the reel, 31 weeks lead time from Mouser.
>>>>>>>
>>>>>>> Avnet has none, for $6.50 by the reel.
>>>>>>
>>>>>> I do happen to like ECL. LVDS works much the same way.
>>>>>
>>>>> TinyLogic CMOS parts are as fast as 10K ECL used to be, for a few per
>>>>> cent of the cost and power dissipation. Internally, logic inside an
>>>>> FPGA is far faster than 10EL or 10EP. And maybe 10,000 times cheaper.
>>>>
>>>> 10k ECL is still around. 100k is just as fast and better behaved and
>>>> ECLinPS has been faster since the 1990's. It isn't cheap because it has
>>>> never been a mass market product. Getting digital engineers to pay
>>>> attention to what happen in a transmission line turns out to be quite
>>>> difficult.
>>>>
>>>> Burying the fast stuff in the confined dimensions of a single FPGA
>>>> mostly evades that problem.
>>>>
>>>>> My 50-cent DDS frequency systhesizer is clocked at 250 MHz, and uses
>>>>> about 20 milliwatts.
>>>>
>>>> But does it have any high frequency outputs?
>>>
>>> We're synthesizing an octave, probably 20 to 40 MHz, way below
>>> Nyquist, and then dividing down as needed. Limiting it to one octave
>>> keeps the passive LC filter simple.
>>>
>>> A simple NCO, using the MSB of a phase accumulator, has 4 ns p-p
>>> jitter with a 250 MHz clock. That's actually got interesting
>>> statistics.
>>>
>>> Adding the sine lookup and the dumb DAC and the lowpass filter and
>>> comparator reduces the period jitter by at least 20:1.
>>
>> As it should.The comparator is essentially looking at 4nsec long almost linear ramp between DAC output changes.
>>
>>> The math is out of my league so we are designing mostly with
>>> simulation and solder.
>>
>> Insight could also be useful, if you could achieve it.
>>
>
> Indeed. Can *you* provide us with such insight?

Bill couldn't get below 60dB with over 60 components.
The circuit below is comfortably 100dB in simulation with only 18 components.

Version 4.1
SHEET 1 3020 1796
WIRE -176 -208 -288 -208
WIRE 0 -208 -96 -208
WIRE 96 -208 0 -208
WIRE 224 -208 96 -208
WIRE 400 -208 304 -208
WIRE 0 -176 0 -208
WIRE 96 -176 96 -208
WIRE 0 -80 0 -112
WIRE 48 -80 0 -80
WIRE 96 -80 96 -112
WIRE 96 -80 48 -80
WIRE 48 -48 48 -80
WIRE -288 32 -288 -208
WIRE -176 32 -288 32
WIRE -32 32 -96 32
WIRE 48 32 -32 32
WIRE 208 32 128 32
WIRE 256 32 208 32
WIRE 400 32 400 -208
WIRE 400 32 320 32
WIRE 464 32 400 32
WIRE 608 32 544 32
WIRE 656 32 608 32
WIRE 800 32 720 32
WIRE -288 144 -288 32
WIRE -176 144 -288 144
WIRE 208 144 208 32
WIRE 256 144 208 144
WIRE 608 144 608 32
WIRE 656 144 608 144
WIRE -32 160 -32 32
WIRE -32 160 -112 160
WIRE 400 160 400 32
WIRE 400 160 320 160
WIRE 800 160 800 32
WIRE 800 160 720 160
WIRE 832 160 800 160
WIRE 944 160 912 160
WIRE 992 160 944 160
WIRE 1120 160 1072 160
WIRE 1184 160 1120 160
WIRE 1328 160 1264 160
WIRE 1392 160 1328 160
WIRE 1424 160 1392 160
WIRE -176 176 -240 176
WIRE 256 176 224 176
WIRE 656 176 624 176
WIRE 224 208 224 176
WIRE 624 208 624 176
WIRE 944 272 944 160
WIRE 992 272 944 272
WIRE 1120 272 1120 160
WIRE 1120 272 1056 272
WIRE 1184 272 1120 272
WIRE -240 288 -240 176
WIRE -176 288 -240 288
WIRE 400 288 400 160
WIRE 400 288 -96 288
WIRE 1328 288 1328 160
WIRE 1328 288 1248 288
WIRE 1184 304 1120 304
WIRE -240 336 -240 288
WIRE 1120 336 1120 304
WIRE -448 352 -448 320
WIRE -448 352 -496 352
WIRE -496 368 -496 352
WIRE -32 368 -32 160
WIRE 832 368 -32 368
WIRE 944 368 944 272
WIRE 944 368 912 368
WIRE -448 384 -448 352
WIRE -240 448 -240 416
WIRE -288 512 -288 144
WIRE 80 512 -288 512
WIRE 800 512 800 160
WIRE 800 512 160 512
FLAG 224 208 0
FLAG 624 208 0
FLAG -496 368 0
FLAG -448 240 vcc
FLAG -448 464 vee
FLAG -144 128 vcc
FLAG -144 192 vee
FLAG 288 128 vcc
FLAG 288 192 vee
FLAG 688 128 vcc
FLAG 688 192 vee
FLAG 48 -48 0
FLAG 1216 256 vcc
FLAG 1216 320 vee
FLAG 1120 336 0
FLAG 1392 160 vout
FLAG -240 448 0
SYMBOL res -80 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 144 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 16K
SYMBOL res 560 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 16K
SYMBOL cap 320 16 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL cap 720 16 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL res 176 496 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL voltage -448 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 15
SYMBOL voltage -448 368 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 15
SYMBOL OpAmps\\LT1679 -144 160 R0
SYMATTR InstName U5
SYMBOL OpAmps\\LT1679 288 160 R0
SYMATTR InstName U6
SYMBOL OpAmps\\LT1679 688 160 R0
SYMATTR InstName U8
SYMBOL res -80 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R8
SYMATTR Value 10k
SYMBOL res -256 320 R0
SYMATTR InstName R9
SYMATTR Value 470
SYMBOL diode -16 -176 R0
SYMATTR InstName D1
SYMATTR Value 1N914
SYMBOL diode 80 -112 M180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMATTR Value 1N914
SYMBOL res -80 -224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 47k
SYMBOL res 320 -224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 47k
SYMBOL res 928 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 1k
SYMBOL res 928 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R10
SYMATTR Value 9.1k
SYMBOL res 1280 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R11
SYMATTR Value 4.7k
SYMBOL OpAmps\\LT1679 1216 288 R0
SYMATTR InstName U1
SYMBOL ind 1088 144 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L1
SYMATTR Value 68m
SYMATTR SpiceLine Ipk=0.05 Rser Rparp9600 Cpar.406p mfg="Würth Elektronik" pn="7447452683 WE-TI 8012"
SYMBOL cap 1056 256 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 15n
TEXT -456 576 Left 2 !.tran 0 10 0 100n startup
TEXT -456 632 Left 2 !.options plotwinsize=0 numdgt
TEXT -280 -344 Left 2 ;1KHz 100dB based on https://sound-au.com/articles/sinewave.htm#s51 Fig 5.1.2\nER May 2026




>
> Jeroen Belleman

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Thread

TCLE john larkin <jl@glen--canyon.com> - 2026-05-03 07:09 -0700
  Re: TCLE Bill Sloman <bill.sloman@ieee.org> - 2026-05-04 01:19 +1000
    Re: TCLE john larkin <jl@glen--canyon.com> - 2026-05-03 10:05 -0700
      Re: TCLE Bill Sloman <bill.sloman@ieee.org> - 2026-05-04 17:06 +1000
        Re: TCLE john larkin <jl@glen--canyon.com> - 2026-05-04 04:19 -0700
          Re: TCLE Bill Sloman <bill.sloman@ieee.org> - 2026-05-05 03:13 +1000
            Re: TCLE john larkin <jl@glen--canyon.com> - 2026-05-04 12:08 -0700
              Re: TCLE Jan Panteltje <alien@comet.invalid> - 2026-05-05 06:54 +0000
                Re: TCLE john larkin <jl@glen--canyon.com> - 2026-05-05 07:34 -0700
                Re: TCLE Jan Panteltje <alien@comet.invalid> - 2026-05-05 16:57 +0000
              Re: TCLE Bill Sloman <bill.sloman@ieee.org> - 2026-05-05 17:29 +1000
                Re: TCLE Jeroen Belleman <jeroen@nospam.please> - 2026-05-05 12:40 +0200
                Re: TCLE "Edward Rawde" <invalid@invalid.invalid> - 2026-05-05 09:58 -0400
                Re: TCLE "Edward Rawde" <invalid@invalid.invalid> - 2026-05-05 10:09 -0400
                Re: TCLE "Edward Rawde" <invalid@invalid.invalid> - 2026-05-05 10:10 -0400
                Re: TCLE Bill Sloman <bill.sloman@ieee.org> - 2026-05-06 02:30 +1000
                Re: TCLE "Edward Rawde" <invalid@invalid.invalid> - 2026-05-05 12:46 -0400
                Re: TCLE piglet <erichpwagner@hotmail.com> - 2026-05-05 19:44 +0100
                Re: TCLE "Edward Rawde" <invalid@invalid.invalid> - 2026-05-05 15:30 -0400
                Re: TCLE Jeroen Belleman <jeroen@nospam.please> - 2026-05-05 18:37 +0200
                Re: TCLE Bill Sloman <bill.sloman@ieee.org> - 2026-05-06 02:15 +1000
                Re: TCLE john larkin <jl@glen--canyon.com> - 2026-05-05 07:41 -0700
                Re: TCLE Bill Sloman <bill.sloman@ieee.org> - 2026-05-06 02:38 +1000
                Re: TCLE john larkin <jl@glen--canyon.com> - 2026-05-05 11:52 -0700
                Re: TCLE Bill Sloman <bill.sloman@ieee.org> - 2026-05-08 04:25 +1000
                Re: TCLE john larkin <jl@glen--canyon.com> - 2026-05-07 13:14 -0700
                Re: TCLE Bill Sloman <bill.sloman@ieee.org> - 2026-05-08 15:03 +1000
                Re: TCLE john larkin <jl@glen--canyon.com> - 2026-05-08 03:26 -0700
                Re: TCLE Bill Sloman <bill.sloman@ieee.org> - 2026-05-08 22:26 +1000
  Re: TCLE Lasse Langwadt <llc@fonz.dk> - 2026-05-03 19:12 +0200
    Re: TCLE john larkin <jl@glen--canyon.com> - 2026-05-03 12:01 -0700
      Re: TCLE Lasse Langwadt <llc@fonz.dk> - 2026-05-04 23:30 +0200
        Re: TCLE john larkin <jl@glen--canyon.com> - 2026-05-04 15:06 -0700
          Re: TCLE Lasse Langwadt <llc@fonz.dk> - 2026-05-05 00:50 +0200
            Re: TCLE john larkin <jl@glen--canyon.com> - 2026-05-04 15:58 -0700
              Re: TCLE Bill Sloman <bill.sloman@ieee.org> - 2026-05-05 17:36 +1000
                Re: TCLE john larkin <jl@glen--canyon.com> - 2026-05-05 11:48 -0700
                Re: TCLE Bill Sloman <bill.sloman@ieee.org> - 2026-05-06 18:45 +1000
                Re: TCLE Lasse Langwadt <llc@fonz.dk> - 2026-05-05 22:55 +0200
              Re: TCLE someone <2a59d59e3809f827ce709d3815e3950eef4a6a93af5557a93a7fdfba71460843@example.com> - 2026-05-05 18:15 +0000
                Re: TCLE john larkin <jl@glen--canyon.com> - 2026-05-05 11:38 -0700
                Re: TCLE Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> - 2026-05-05 19:25 +0000
                Re: TCLE john larkin <jl@glen--canyon.com> - 2026-05-05 13:41 -0700
                Re: TCLE Lasse Langwadt <llc@fonz.dk> - 2026-05-06 00:05 +0200
                Re: TCLE Gerhard Hoffmann <dk4xp@arcor.de> - 2026-05-05 21:09 +0200
  Re: TCLE "Edward Rawde" <invalid@invalid.invalid> - 2026-05-03 15:49 -0400

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