Re: Can someone explain step by step how one avoid many conditional in forth as described in Moore Fourth essay?

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Date	Fri, 13 Jan 2012 10:09:03 -0800
From	"Andy (Super) Glew" <andy@SPAM.comp-arch.net>
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Subject	Re: Can someone explain step by step how one avoid many conditional in forth as described in Moore Fourth essay?
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On 1/13/2012 9:47 AM, Joe keane wrote:
> In article<4F0DC609.9020503@SPAM.comp-arch.net>,
> Andy (Super) Glew<andy@SPAM.comp-arch.net>  wrote:
>> I believe an IBM chip did eager ifetch - fetching both sides of a
>> branch - but did not actually execute, stalled at decoder or
>> therabouts.
>
> Doing some 'early' loads seems like a good idea, assuming that you have
> some IF units free.
>
> But that is a *lot* different from the other suggestion, copying the
> machine state to a different core.

Microarchitectures proposed for eager execution:

* using the same pipeline(s) as ordinary non-eager
** e.g. if stalled on the main path, execute on the alternative path
** DEE: e.g. if have gone too far down one path, execute on an 
alternative path that has higher relative probability of success than 
predicting yet another branch on the current path.

Actually, the DEE technique applies to all forms of eager execution.

* using eager threads on the same CPU core
** although not necessarily the same pipeline(s) - eager threading was 
one of the techniques I wanted to investigate on top of my multicluster 
multithreading (MCMT) substrate -- although in my experience eager 
nearly always loses out to non-eager forms of speculation.

Note that this is not necessarily the same pipeline resources, since in 
my terminology an MCMT machine like Bulldozer is really a single CPU 
with multiple execution clusters.

* using eager threads of execution on different CPU cores.

Problem is that eager threads seldom last long, so it is hard for eager 
threads to overcome the cost of migrating to another core.

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