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PCIe Interrupt handling

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Hello Experts,

I'm writing driver for pcie xilinx fpga. The fpga hardware team has
not given me any interrupt status register, interrupt enable register.
They just said to set the bit 9 in the device control register which
would enable the interrupt(for read or write completion). Is this
sufficient to handle the interrupts? When I register the interrupt
with a shared flag, my handler gets called even when the bit 9 is
reset, how do i make sure if the appropriate interrupt is being
received? How do i control it? Do i need to request the fpga hardware
to add any extra registers?

please help.

Thanks a ton.

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PCIe Interrupt handling new <luvraghu@gmail.com> - 2011-06-29 06:42 -0700

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