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Groups > comp.lang.c++ > #118058 > unrolled thread
| Started by | Bonita Montero <Bonita.Montero@gmail.com> |
|---|---|
| First post | 2023-12-10 10:46 +0100 |
| Last post | 2024-02-14 15:57 +0100 |
| Articles | 20 on this page of 213 — 14 participants |
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Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-10 10:46 +0100
Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2023-12-10 21:48 +0000
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-11 04:15 +0100
Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2023-12-11 17:12 +0000
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-11 18:19 +0100
Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2023-12-13 15:16 +0000
Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2023-12-13 15:25 +0000
Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2023-12-14 15:06 +0000
Re: Sieve of Erastosthenes optimized to the max red floyd <no.spam.here@its.invalid> - 2023-12-14 08:20 -0800
Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2023-12-23 10:30 -0800
Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2023-12-23 21:20 +0000
Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2023-12-24 00:36 -0800
Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2023-12-29 18:03 +0000
Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-01-13 21:31 -0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-20 13:44 +0100
Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2023-12-21 15:30 +0000
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-21 17:07 +0100
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-21 17:13 +0100
Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2023-12-23 10:21 -0800
Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2023-12-23 21:21 +0000
Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2023-12-24 10:49 -0800
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2023-12-21 14:23 -0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-22 04:28 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2023-12-21 20:02 -0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-22 17:55 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2023-12-23 12:52 -0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-24 11:03 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2023-12-24 13:24 -0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-26 06:00 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2023-12-25 21:39 -0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-26 10:27 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2023-12-26 12:24 -0800
Re: Sieve of Erastosthenes optimized to the max Kaz Kylheku <433-929-6894@kylheku.com> - 2023-12-26 23:35 +0000
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2023-12-26 15:37 -0800
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2023-12-26 21:59 -0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-27 10:23 +0100
Re: Sieve of Erastosthenes optimized to the max Kaz Kylheku <433-929-6894@kylheku.com> - 2023-12-27 20:49 +0000
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-28 12:00 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2023-12-28 15:38 -0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-29 04:17 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2023-12-28 20:58 -0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-29 10:58 +0100
Re: Sieve of Erastosthenes optimized to the max David Brown <david.brown@hesbynett.no> - 2023-12-29 13:56 +0100
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-29 17:04 +0100
Re: Sieve of Erastosthenes optimized to the max David Brown <david.brown@hesbynett.no> - 2023-12-30 19:27 +0100
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-31 11:22 +0100
Re: Sieve of Erastosthenes optimized to the max scott@slp53.sl.home (Scott Lurndal) - 2023-12-31 18:49 +0000
Re: Sieve of Erastosthenes optimized to the max David Brown <david.brown@hesbynett.no> - 2024-01-01 12:46 +0100
Re: Sieve of Erastosthenes optimized to the max scott@slp53.sl.home (Scott Lurndal) - 2023-12-29 16:01 +0000
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-29 17:06 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2023-12-29 13:45 -0800
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2023-12-29 14:09 -0800
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2023-12-29 14:12 -0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-30 05:42 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2023-12-29 20:45 -0800
Re: Sieve of Erastosthenes optimized to the max Kaz Kylheku <433-929-6894@kylheku.com> - 2023-12-30 04:56 +0000
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-30 06:09 +0100
Re: Sieve of Erastosthenes optimized to the max Kaz Kylheku <433-929-6894@kylheku.com> - 2023-12-30 05:51 +0000
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-30 10:15 +0100
Re: Sieve of Erastosthenes optimized to the max Kaz Kylheku <433-929-6894@kylheku.com> - 2023-12-30 20:35 +0000
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-31 06:54 +0100
Re: Sieve of Erastosthenes optimized to the max Kaz Kylheku <433-929-6894@kylheku.com> - 2023-12-31 07:01 +0000
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-31 11:20 +0100
Re: Sieve of Erastosthenes optimized to the max Kaz Kylheku <433-929-6894@kylheku.com> - 2023-12-31 17:30 +0000
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-01-01 06:21 +0100
Re: Sieve of Erastosthenes optimized to the max scott@slp53.sl.home (Scott Lurndal) - 2023-12-31 18:44 +0000
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-01-01 06:22 +0100
Re: Sieve of Erastosthenes optimized to the max Kaz Kylheku <433-929-6894@kylheku.com> - 2024-01-01 08:28 +0000
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-01-01 14:11 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2024-01-01 15:36 -0800
Re: Sieve of Erastosthenes optimized to the max Kaz Kylheku <433-929-6894@kylheku.com> - 2023-12-30 04:51 +0000
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2023-12-30 12:00 -0800
Re: Sieve of Erastosthenes optimized to the max Kaz Kylheku <433-929-6894@kylheku.com> - 2023-12-29 17:29 +0000
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-30 05:45 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2023-12-30 11:58 -0800
Re: Sieve of Erastosthenes optimized to the max red floyd <no.spam.here@its.invalid> - 2023-12-30 14:58 -0800
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2023-12-31 11:49 -0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-31 06:51 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2023-12-31 11:36 -0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-01-01 07:28 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2023-12-31 22:53 -0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-01-01 14:11 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2024-01-01 15:34 -0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-01-02 11:55 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2024-01-02 10:38 -0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-01-03 06:48 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2024-01-03 13:32 -0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-01-04 04:37 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2024-01-05 19:21 -0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-01-06 08:18 +0100
Re: Sieve of Erastosthenes optimized to the max Kaz Kylheku <433-929-6894@kylheku.com> - 2024-01-06 08:31 +0000
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-01-06 10:30 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2024-01-06 13:15 -0800
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2024-01-06 13:19 -0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-01-07 10:14 +0100
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-01-07 10:10 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2024-01-07 12:46 -0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-01-08 06:48 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2024-01-08 12:18 -0800
Re: Sieve of Erastosthenes optimized to the max red floyd <no.spam.here@its.invalid> - 2024-01-08 17:14 -0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-01-09 07:19 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2024-01-09 23:33 -0800
Re: Sieve of Erastosthenes optimized to the max Kaz Kylheku <433-929-6894@kylheku.com> - 2024-01-09 02:02 +0000
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-01-09 15:12 +0100
OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) Vir Campestris <vir.campestris@invalid.invalid> - 2024-01-29 21:31 +0000
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-02-16 08:06 -0800
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) Bonita Montero <Bonita.Montero@gmail.com> - 2024-02-16 18:30 +0100
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-02-23 05:51 -0800
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) Bonita Montero <Bonita.Montero@gmail.com> - 2024-02-24 10:45 +0100
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-02-25 00:48 -0800
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) Bonita Montero <Bonita.Montero@gmail.com> - 2024-02-25 15:51 +0100
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-03-11 10:10 -0700
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) Bonita Montero <Bonita.Montero@gmail.com> - 2024-03-12 10:15 +0100
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) wij <wyniijj5@gmail.com> - 2024-03-14 12:44 +0800
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) Bonita Montero <Bonita.Montero@gmail.com> - 2024-03-14 07:25 +0100
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) wij <wyniijj5@gmail.com> - 2024-03-14 17:20 +0800
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) wij <wyniijj5@gmail.com> - 2024-03-14 17:35 +0800
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) wij <wyniijj5@gmail.com> - 2024-03-14 17:41 +0800
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) Bonita Montero <Bonita.Montero@gmail.com> - 2024-03-14 19:20 +0100
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) wij <wyniijj5@gmail.com> - 2024-03-15 16:30 +0800
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) Bonita Montero <Bonita.Montero@gmail.com> - 2024-03-15 11:21 +0100
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) wij <wyniijj5@gmail.com> - 2024-03-15 19:07 +0800
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) Bonita Montero <Bonita.Montero@gmail.com> - 2024-03-15 12:56 +0100
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) Bonita Montero <Bonita.Montero@gmail.com> - 2024-03-14 19:20 +0100
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-04-20 08:35 -0700
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) Bonita Montero <Bonita.Montero@gmail.com> - 2024-04-20 18:34 +0200
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) Bonita Montero <Bonita.Montero@gmail.com> - 2024-04-20 18:35 +0200
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-04-24 12:28 -0700
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) Bonita Montero <Bonita.Montero@gmail.com> - 2024-04-25 06:19 +0200
Re: OT: A better sieve (was Re: Sieve of Erastosthenes optimized to the max) Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-04-25 14:14 -0700
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2023-12-31 11:39 -0800
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2023-12-29 13:52 -0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2023-12-27 06:06 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2024-03-22 19:34 -0700
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-03-23 17:54 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2024-03-23 14:04 -0700
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-03-24 07:30 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2024-03-24 12:52 -0700
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-03-24 21:00 +0100
Re: Sieve of Erastosthenes optimized to the max "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2024-03-24 13:05 -0700
Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2024-05-16 17:28 +0100
Re: Sieve of Erastosthenes optimized to the max Ben Bacarisse <ben@bsb.me.uk> - 2024-05-16 21:40 +0100
Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-05-21 19:06 -0700
Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2024-05-30 12:32 +0100
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-05-30 14:17 +0200
Re: Sieve of Erastosthenes optimized to the max Paavo Helde <eesnimi@osa.pri.ee> - 2024-05-30 19:55 +0300
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-05-31 10:17 +0200
Re: Sieve of Erastosthenes optimized to the max Paavo Helde <eesnimi@osa.pri.ee> - 2024-05-31 20:52 +0300
Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-05-30 22:17 -0700
Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2024-06-01 21:07 +0100
Re: Sieve of Erastosthenes optimized to the max Richard Damon <richard@damon-family.org> - 2024-06-01 20:43 -0400
Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-06-02 03:23 -0700
Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-06-02 19:50 -0700
Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2024-06-18 20:56 +0100
Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-06-18 17:34 -0700
Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2024-06-30 21:47 +0100
Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-07-01 23:20 -0700
Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2024-07-02 21:24 +0100
Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2024-07-03 11:25 +0100
Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-07-15 06:15 -0700
Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-07-20 07:41 -0700
OT: Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2024-07-25 12:46 +0100
Re: OT: Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-08-10 07:07 -0700
Re: OT: Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2024-08-12 15:32 +0100
Re: OT: Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-08-16 07:48 -0700
Re: OT: Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2024-08-15 17:52 +0100
Re: OT: Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-08-16 08:40 -0700
Re: OT: Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-08-16 19:35 +0200
Re: OT: Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-08-16 19:55 +0200
Re: OT: Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2024-08-19 21:23 +0100
Re: OT: Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-08-20 17:21 +0200
Re: OT: Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-08-20 17:24 +0200
Re: OT: Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-08-20 17:43 +0200
Re: OT: Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2024-08-20 17:55 +0100
Re: OT: Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-08-20 18:59 +0200
Re: OT: Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-08-26 12:08 -0700
Re: OT: Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-08-27 06:09 +0200
Re: OT: Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2024-09-01 21:23 +0100
Re: OT: Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-09-01 20:40 -0700
Re: OT: Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-09-02 07:08 +0200
Re: OT: Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2024-09-03 17:45 +0100
Re: OT: Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-09-28 03:46 -0700
Re: OT: Re: Sieve of Erastosthenes optimized to the max Keith Thompson <Keith.S.Thompson+u@gmail.com> - 2024-09-28 13:49 -0700
Re: OT: Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2024-10-02 11:44 +0100
Re: OT: Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-10-02 13:10 +0200
Re: OT: Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-10-07 08:41 -0700
Re: OT: Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2024-10-20 12:44 +0100
Re: OT: Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-11-04 03:56 -0800
Re: OT: Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2024-08-19 21:34 +0100
Re: OT: Re: Sieve of Erastosthenes optimized to the max red floyd <no.spam.here@its.invalid> - 2024-08-19 21:08 -0700
Re: OT: Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2024-08-20 21:14 +0100
Re: OT: Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-08-26 09:35 -0700
Re: OT: Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-08-26 08:31 -0700
Re: OT: Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-08-20 19:20 +0200
Re: OT: Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-08-20 19:36 +0200
Re: OT: Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-08-20 19:39 +0200
Re: OT: Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-08-20 20:13 +0200
Re: OT: Re: Sieve of Erastosthenes optimized to the max scott@slp53.sl.home (Scott Lurndal) - 2024-08-20 20:50 +0000
Re: OT: Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2024-08-22 17:30 +0100
Re: OT: Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-08-22 18:38 +0200
Re: OT: Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2024-08-22 21:47 +0100
Re: OT: Re: Sieve of Erastosthenes optimized to the max Vir Campestris <vir.campestris@invalid.invalid> - 2024-08-22 21:56 +0100
Re: OT: Re: Sieve of Erastosthenes optimized to the max red floyd <no.spam.here@its.invalid> - 2024-08-22 17:00 -0700
Re: OT: Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-08-26 10:59 -0700
Re: OT: Re: Sieve of Erastosthenes optimized to the max Andrey Tarasevich <andreytarasevich@hotmail.com> - 2024-09-28 15:21 -0700
Re: OT: Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-08-26 12:47 -0700
Re: OT: Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-08-18 19:52 -0700
Re: OT: Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-08-10 17:24 -0700
Re: OT: Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-08-11 00:00 -0700
Re: Sieve of Erastosthenes optimized to the max Tim Rentsch <tr.17687@z991.linuxsc.com> - 2024-07-23 07:34 -0700
Re: Sieve of Erastosthenes optimized to the max wij <wyniijj5@gmail.com> - 2024-02-14 00:15 +0800
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-02-13 19:08 +0100
Re: Sieve of Erastosthenes optimized to the max Bonita Montero <Bonita.Montero@gmail.com> - 2024-02-14 15:57 +0100
Page 5 of 11 — ← Prev page 1 … 3 4 [5] 6 7 … 11 Next page →
| From | "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> |
|---|---|
| Date | 2023-12-31 22:53 -0800 |
| Message-ID | <umtnhl$234ro$1@dont-email.me> |
| In reply to | #118183 |
On 12/31/2023 10:28 PM, Bonita Montero wrote: > Am 31.12.2023 um 20:36 schrieb Chris M. Thomasson: > >>> I'm pretty sure they never ran the numbers on that. > >> I am pretty sure you are trolling, Bonita? > > If you allocate memory the memory usually comes from a pool > where theset indices of the memory block are rather randomized. > It's rather unlikey that you'd get set conflicts with the both > thread to an extent that this really hurts performance. > Oh my. You really did not read the paper I linked to up thread!
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| From | Bonita Montero <Bonita.Montero@gmail.com> |
|---|---|
| Date | 2024-01-01 14:11 +0100 |
| Message-ID | <umudmb$27da9$2@raubtier-asyl.eternal-september.org> |
| In reply to | #118184 |
Am 01.01.2024 um 07:53 schrieb Chris M. Thomasson: > Oh my. You really did not read the paper I linked to up thread! The suggestion Intel made here is just a Nerd-suggestion and you're a nerd as well.
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| From | "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> |
|---|---|
| Date | 2024-01-01 15:34 -0800 |
| Message-ID | <umvi6u$2c9ue$1@dont-email.me> |
| In reply to | #118188 |
On 1/1/2024 5:11 AM, Bonita Montero wrote: > Am 01.01.2024 um 07:53 schrieb Chris M. Thomasson: > >> Oh my. You really did not read the paper I linked to up thread! > > The suggestion Intel made here is just a Nerd-suggestion and > you're a nerd as well. > LOL! Wow, you are the king of interesting responses! :^) Happy New Year!
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| From | Bonita Montero <Bonita.Montero@gmail.com> |
|---|---|
| Date | 2024-01-02 11:55 +0100 |
| Message-ID | <un0q3n$2ks6a$1@raubtier-asyl.eternal-september.org> |
| In reply to | #118189 |
Am 02.01.2024 um 00:34 schrieb Chris M. Thomasson: > On 1/1/2024 5:11 AM, Bonita Montero wrote: >> Am 01.01.2024 um 07:53 schrieb Chris M. Thomasson: >> >>> Oh my. You really did not read the paper I linked to up thread! >> >> The suggestion Intel made here is just a Nerd-suggestion and >> you're a nerd as well. >> > > LOL! Wow, you are the king of interesting responses! You consider this suggestion to be important because it makes you feel important.
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| From | "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> |
|---|---|
| Date | 2024-01-02 10:38 -0800 |
| Message-ID | <un1l6g$2q1iv$1@dont-email.me> |
| In reply to | #118191 |
On 1/2/2024 2:55 AM, Bonita Montero wrote: > Am 02.01.2024 um 00:34 schrieb Chris M. Thomasson: >> On 1/1/2024 5:11 AM, Bonita Montero wrote: >>> Am 01.01.2024 um 07:53 schrieb Chris M. Thomasson: >>> >>>> Oh my. You really did not read the paper I linked to up thread! >>> >>> The suggestion Intel made here is just a Nerd-suggestion and >>> you're a nerd as well. >>> >> >> LOL! Wow, you are the king of interesting responses! > > You consider this suggestion to be important because it makes > you feel important. > Not true. Don't project on me, oh holy one. Now, I was reading all of the Intel optimization guides and using VTune at the time, early 2000's. I happened to remember this one (64k aliasing problem), and even found my own C code on the wayback machine that used it. Just because you have not read them does not make me feel "important". You silly rabbit! Tricks are for kids. :^)
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| From | Bonita Montero <Bonita.Montero@gmail.com> |
|---|---|
| Date | 2024-01-03 06:48 +0100 |
| Message-ID | <un2sel$33tna$1@raubtier-asyl.eternal-september.org> |
| In reply to | #118192 |
Am 02.01.2024 um 19:38 schrieb Chris M. Thomasson: > On 1/2/2024 2:55 AM, Bonita Montero wrote: >> Am 02.01.2024 um 00:34 schrieb Chris M. Thomasson: >>> On 1/1/2024 5:11 AM, Bonita Montero wrote: >>>> Am 01.01.2024 um 07:53 schrieb Chris M. Thomasson: >>>> >>>>> Oh my. You really did not read the paper I linked to up thread! >>>> >>>> The suggestion Intel made here is just a Nerd-suggestion and >>>> you're a nerd as well. >>>> >>> >>> LOL! Wow, you are the king of interesting responses! >> >> You consider this suggestion to be important because it makes >> you feel important. >> > > Not true. Don't project on me, oh holy one. I know you in this point - very good. > Now, I was reading all of the Intel optimization guides and using VTune > at the time, early 2000's. I happened to remember this one (64k aliasing > problem), ... There is no 64kB aliasing problem with the L1-cache since the cache is smaller.
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| From | "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> |
|---|---|
| Date | 2024-01-03 13:32 -0800 |
| Message-ID | <un4jos$3ba8u$1@dont-email.me> |
| In reply to | #118193 |
On 1/2/2024 9:48 PM, Bonita Montero wrote: > Am 02.01.2024 um 19:38 schrieb Chris M. Thomasson: >> On 1/2/2024 2:55 AM, Bonita Montero wrote: >>> Am 02.01.2024 um 00:34 schrieb Chris M. Thomasson: >>>> On 1/1/2024 5:11 AM, Bonita Montero wrote: >>>>> Am 01.01.2024 um 07:53 schrieb Chris M. Thomasson: >>>>> >>>>>> Oh my. You really did not read the paper I linked to up thread! >>>>> >>>>> The suggestion Intel made here is just a Nerd-suggestion and >>>>> you're a nerd as well. >>>>> >>>> >>>> LOL! Wow, you are the king of interesting responses! >>> >>> You consider this suggestion to be important because it makes >>> you feel important. >>> >> >> Not true. Don't project on me, oh holy one. > > I know you in this point - very good. > >> Now, I was reading all of the Intel optimization guides and using >> VTune at the time, early 2000's. I happened to remember this one (64k >> aliasing problem), ... > > There is no 64kB aliasing problem with the L1-cache since the cache > is smaller. > Oh god. Have you not read the paper yet? If you have read it all, then you do not seem to understand it at all. That's on you, Bonita. Like I said you need to write Intel a letter telling them how that paper never needed to be written. Lol! You make me laugh! :^)
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| From | Bonita Montero <Bonita.Montero@gmail.com> |
|---|---|
| Date | 2024-01-04 04:37 +0100 |
| Message-ID | <un594t$3hn5o$1@raubtier-asyl.eternal-september.org> |
| In reply to | #118194 |
Am 03.01.2024 um 22:32 schrieb Chris M. Thomasson: > On 1/2/2024 9:48 PM, Bonita Montero wrote: >> There is no 64kB aliasing problem with the L1-cache since the cache >> is smaller. > Oh god. Have you not read the paper yet? ... The Pentium 4's L1 data cache is between 16 and 32kB, so there can't be a 64kB aliasing. And aliasing can be only on a set basis and the sets are 4kB or 8kB large.
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| From | "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> |
|---|---|
| Date | 2024-01-05 19:21 -0800 |
| Message-ID | <unagvf$ft9g$1@dont-email.me> |
| In reply to | #118196 |
On 1/3/2024 7:37 PM, Bonita Montero wrote: > Am 03.01.2024 um 22:32 schrieb Chris M. Thomasson: > >> On 1/2/2024 9:48 PM, Bonita Montero wrote: > >>> There is no 64kB aliasing problem with the L1-cache since the cache >>> is smaller. > >> Oh god. Have you not read the paper yet? ... > > > The Pentium 4's L1 data cache is between 16 and 32kB, so there > can't be a 64kB aliasing. And aliasing can be only on a set basis > and the sets are 4kB or 8kB large. > Are you trying to tell me that the aliasing problem on those older Intel hyperthreaded processors and the workaround (from Intel) was a myth? lol. ;^)
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| From | Bonita Montero <Bonita.Montero@gmail.com> |
|---|---|
| Date | 2024-01-06 08:18 +0100 |
| Message-ID | <unaus6$h9l0$1@raubtier-asyl.eternal-september.org> |
| In reply to | #118198 |
Am 06.01.2024 um 04:21 schrieb Chris M. Thomasson: > Are you trying to tell me that the aliasing problem on those older Intel > hyperthreaded processors and the workaround (from Intel) was a myth? > lol. ;^) Intel just made a nerd-suggestion. With four-way associativity there's no frequent aliasing problem in the L1 data dache of Pentium 4.
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| From | Kaz Kylheku <433-929-6894@kylheku.com> |
|---|---|
| Date | 2024-01-06 08:31 +0000 |
| Message-ID | <20240106000249.177@kylheku.com> |
| In reply to | #118199 |
On 2024-01-06, Bonita Montero <Bonita.Montero@gmail.com> wrote: > Am 06.01.2024 um 04:21 schrieb Chris M. Thomasson: > >> Are you trying to tell me that the aliasing problem on those older Intel >> hyperthreaded processors and the workaround (from Intel) was a myth? >> lol. ;^) > > Intel just made a nerd-suggestion. With four-way associativity > there's no frequent aliasing problem in the L1 data dache of > Pentium 4. I think the L1 cache was 8K on that thing, and the blocks are 32 bytes. I think how it works on the P4 is that the address is structured is like this: 31 11 10 5 4 0 | | | | | | [ 21 bit tag ] [ 6 bit cache set ] [ 5 bit offset into 32 bit block ] Thus say we have an area of the stack with the address range nnnnFF80 to nnnnFFFF (128 bytes, 4 x 32 byte cache blocks). These four blocks all map to the same set: they have the same six bits in the "cache set" part of the address. So if a thread is accessing something in all four blocks, it will completely use that cache set, all by itself. If any other thread has a similar block in its stack, with the same cache set ID, it will cause evictions against this thread. Sure, if each of these threads confines itself to working with just one cacheline-sized aperture of the stack, it looks better. You're forgetting that the sets are very small and that groups of adjacent four 32 byte blocks map to the same set. Touch four adjacent cache blocks that are aligned on a 128 byte boundary, and you have hit full occupancy in the cache set corresponding to that block! (I suspect the references to 64K should not be kilobytes but sets. The 8K cache has 64 sets.) In memory, 128 byte blocks that is aligned maps to, and precisely covers a cache set. If two such blocks addresses that are equal modulo 8K, they collide to the same cache set. If one of those blocks is fully present in the cache, the other must be fully evicted. It's really easy to see how things can go south under hyperthreading. If two hyperthreads are working with clashing 128 byte areas that each want to hog the same cache set, and the core is switching between them on a fine-grained basis, ... you get the picture. It's very easy for the memory mapping allocations used for thread stacks to produce addresses such tha the delta between them is a multiple of 8K. -- TXR Programming Language: http://nongnu.org/txr Cygnal: Cygwin Native Application Library: http://kylheku.com/cygnal Mastodon: @Kazinator@mstdn.ca NOTE: If you use Google Groups, I don't see you, unless you're whitelisted.
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| From | Bonita Montero <Bonita.Montero@gmail.com> |
|---|---|
| Date | 2024-01-06 10:30 +0100 |
| Message-ID | <unb6jc$i4of$1@raubtier-asyl.eternal-september.org> |
| In reply to | #118200 |
Am 06.01.2024 um 09:31 schrieb Kaz Kylheku: > On 2024-01-06, Bonita Montero <Bonita.Montero@gmail.com> wrote: >> Am 06.01.2024 um 04:21 schrieb Chris M. Thomasson: >> >>> Are you trying to tell me that the aliasing problem on those older Intel >>> hyperthreaded processors and the workaround (from Intel) was a myth? >>> lol. ;^) >> >> Intel just made a nerd-suggestion. With four-way associativity >> there's no frequent aliasing problem in the L1 data dache of >> Pentium 4. > > I think the L1 cache was 8K on that thing, and the blocks are 32 bytes. > > I think how it works on the P4 is that the address is structured is like > this: > > 31 11 10 5 4 0 > | | | | | | > [ 21 bit tag ] [ 6 bit cache set ] [ 5 bit offset into 32 bit block ] > > Thus say we have an area of the stack with the address > range nnnnFF80 to nnnnFFFF (128 bytes, 4 x 32 byte cache blocks). > > These four blocks all map to the same set: they have the same six > bits in the "cache set" part of the address. > > So if a thread is accessing something in all four blocks, it will > completely use that cache set, all by itself. > > If any other thread has a similar block in its stack, with the same > cache set ID, it will cause evictions against this thread. > > Sure, if each of these threads confines itself to working with just one > cacheline-sized aperture of the stack, it looks better. > > You're forgetting that the sets are very small and that groups of > adjacent four 32 byte blocks map to the same set. Touch four adjacent > cache blocks that are aligned on a 128 byte boundary, and you have > hit full occupancy in the cache set corresponding to that block! > > (I suspect the references to 64K should not be kilobytes but sets. > The 8K cache has 64 sets.) > > In memory, 128 byte blocks that is aligned maps to, and precisely covers > a cache set. If two such blocks addresses that are equal modulo 8K, they > collide to the same cache set. If one of those blocks is fully present > in the cache, the other must be fully evicted. > > It's really easy to see how things can go south under hyperthreading. > If two hyperthreads are working with clashing 128 byte areas that each > want to hog the same cache set, and the core is switching between them > on a fine-grained basis, ... you get the picture. > > It's very easy for the memory mapping allocations used for thread > stacks to produce addresses such tha the delta between them is a > multiple of 8K. > Of course it's easy to intentionally provoke frequent aliasing with the P4's L1 cache, but actually this doesn't happen often.
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| From | "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> |
|---|---|
| Date | 2024-01-06 13:15 -0800 |
| Message-ID | <uncfue$ojf6$1@dont-email.me> |
| In reply to | #118201 |
On 1/6/2024 1:30 AM, Bonita Montero wrote: > Am 06.01.2024 um 09:31 schrieb Kaz Kylheku: >> On 2024-01-06, Bonita Montero <Bonita.Montero@gmail.com> wrote: >>> Am 06.01.2024 um 04:21 schrieb Chris M. Thomasson: >>> >>>> Are you trying to tell me that the aliasing problem on those older >>>> Intel >>>> hyperthreaded processors and the workaround (from Intel) was a myth? >>>> lol. ;^) >>> >>> Intel just made a nerd-suggestion. With four-way associativity >>> there's no frequent aliasing problem in the L1 data dache of >>> Pentium 4. >> >> I think the L1 cache was 8K on that thing, and the blocks are 32 bytes. >> >> I think how it works on the P4 is that the address is structured is like >> this: >> >> 31 11 10 5 4 0 >> | | | | | | >> [ 21 bit tag ] [ 6 bit cache set ] [ 5 bit offset into 32 bit block ] >> >> Thus say we have an area of the stack with the address >> range nnnnFF80 to nnnnFFFF (128 bytes, 4 x 32 byte cache blocks). >> >> These four blocks all map to the same set: they have the same six >> bits in the "cache set" part of the address. >> >> So if a thread is accessing something in all four blocks, it will >> completely use that cache set, all by itself. >> >> If any other thread has a similar block in its stack, with the same >> cache set ID, it will cause evictions against this thread. >> >> Sure, if each of these threads confines itself to working with just one >> cacheline-sized aperture of the stack, it looks better. >> >> You're forgetting that the sets are very small and that groups of >> adjacent four 32 byte blocks map to the same set. Touch four adjacent >> cache blocks that are aligned on a 128 byte boundary, and you have >> hit full occupancy in the cache set corresponding to that block! >> >> (I suspect the references to 64K should not be kilobytes but sets. >> The 8K cache has 64 sets.) >> >> In memory, 128 byte blocks that is aligned maps to, and precisely covers >> a cache set. If two such blocks addresses that are equal modulo 8K, they >> collide to the same cache set. If one of those blocks is fully present >> in the cache, the other must be fully evicted. >> >> It's really easy to see how things can go south under hyperthreading. >> If two hyperthreads are working with clashing 128 byte areas that each >> want to hog the same cache set, and the core is switching between them >> on a fine-grained basis, ... you get the picture. >> >> It's very easy for the memory mapping allocations used for thread >> stacks to produce addresses such tha the delta between them is a >> multiple of 8K. >> > > > Of course it's easy to intentionally provoke frequent aliasing > with the P4's L1 cache, but actually this doesn't happen often. Fwiw, some people were complaining about bad performance using hyperthreading. Turning it off in bios improved performance. Hence the paper was written to show them how to vastly improve performance when hyperthreading was turned on. You call it nerd stuff, and I still cannot figure out why?
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| From | "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> |
|---|---|
| Date | 2024-01-06 13:19 -0800 |
| Message-ID | <uncg5t$ojf6$2@dont-email.me> |
| In reply to | #118202 |
On 1/6/2024 1:15 PM, Chris M. Thomasson wrote: > On 1/6/2024 1:30 AM, Bonita Montero wrote: >> Am 06.01.2024 um 09:31 schrieb Kaz Kylheku: >>> On 2024-01-06, Bonita Montero <Bonita.Montero@gmail.com> wrote: >>>> Am 06.01.2024 um 04:21 schrieb Chris M. Thomasson: >>>> >>>>> Are you trying to tell me that the aliasing problem on those older >>>>> Intel >>>>> hyperthreaded processors and the workaround (from Intel) was a myth? >>>>> lol. ;^) >>>> >>>> Intel just made a nerd-suggestion. With four-way associativity >>>> there's no frequent aliasing problem in the L1 data dache of >>>> Pentium 4. >>> >>> I think the L1 cache was 8K on that thing, and the blocks are 32 bytes. >>> >>> I think how it works on the P4 is that the address is structured is like >>> this: >>> >>> 31 11 10 5 4 0 >>> | | | | | | >>> [ 21 bit tag ] [ 6 bit cache set ] [ 5 bit offset into 32 bit block ] >>> >>> Thus say we have an area of the stack with the address >>> range nnnnFF80 to nnnnFFFF (128 bytes, 4 x 32 byte cache blocks). >>> >>> These four blocks all map to the same set: they have the same six >>> bits in the "cache set" part of the address. >>> >>> So if a thread is accessing something in all four blocks, it will >>> completely use that cache set, all by itself. >>> >>> If any other thread has a similar block in its stack, with the same >>> cache set ID, it will cause evictions against this thread. >>> >>> Sure, if each of these threads confines itself to working with just one >>> cacheline-sized aperture of the stack, it looks better. >>> >>> You're forgetting that the sets are very small and that groups of >>> adjacent four 32 byte blocks map to the same set. Touch four adjacent >>> cache blocks that are aligned on a 128 byte boundary, and you have >>> hit full occupancy in the cache set corresponding to that block! >>> >>> (I suspect the references to 64K should not be kilobytes but sets. >>> The 8K cache has 64 sets.) >>> >>> In memory, 128 byte blocks that is aligned maps to, and precisely covers >>> a cache set. If two such blocks addresses that are equal modulo 8K, they >>> collide to the same cache set. If one of those blocks is fully present >>> in the cache, the other must be fully evicted. >>> >>> It's really easy to see how things can go south under hyperthreading. >>> If two hyperthreads are working with clashing 128 byte areas that each >>> want to hog the same cache set, and the core is switching between them >>> on a fine-grained basis, ... you get the picture. >>> >>> It's very easy for the memory mapping allocations used for thread >>> stacks to produce addresses such tha the delta between them is a >>> multiple of 8K. >>> >> >> >> Of course it's easy to intentionally provoke frequent aliasing >> with the P4's L1 cache, but actually this doesn't happen often. > > Fwiw, some people were complaining about bad performance using > hyperthreading. Turning it off in bios improved performance. Hence the > paper was written to show them how to vastly improve performance when > hyperthreading was turned on. You call it nerd stuff, and I still cannot > figure out why? Humm... I can see it know. Bonita works for Intel and received the complaints... Bonita says shut up you stupid nerds! Humm... ;^o
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| From | Bonita Montero <Bonita.Montero@gmail.com> |
|---|---|
| Date | 2024-01-07 10:14 +0100 |
| Message-ID | <undq2c$117ni$2@raubtier-asyl.eternal-september.org> |
| In reply to | #118203 |
Am 06.01.2024 um 22:19 schrieb Chris M. Thomasson: > Humm... I can see it know. Bonita works for Intel and received the > complaints... Bonita says shut up you stupid nerds! Humm... ;^o Intel made a number of bad decisions with the Pentium 4 that the architecture was dropped and replaced with a descendant of Pentium 3, whose descendants are still in current Intel CPUs today. In this respect, not only was the architecture bad, but also the documenta- tion, because it is certainly very rare that moving the stack of a thread when threads are running synchronously is of any use.
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| From | Bonita Montero <Bonita.Montero@gmail.com> |
|---|---|
| Date | 2024-01-07 10:10 +0100 |
| Message-ID | <undpp4$117ni$1@raubtier-asyl.eternal-september.org> |
| In reply to | #118202 |
Am 06.01.2024 um 22:15 schrieb Chris M. Thomasson: > Fwiw, some people were complaining about bad performance using > hyperthreading. Turning it off in bios improved performance. > Hence the paper was written to show them how to vastly improve > performance when hyperthreading was turned on. You call it nerd > stuff, and I still cannot figure out why? We were talking about mutual cache flushing and you don't kow that this was the issue with switching of hyperthreading.
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| From | "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> |
|---|---|
| Date | 2024-01-07 12:46 -0800 |
| Message-ID | <unf2ip$16tqc$1@dont-email.me> |
| In reply to | #118204 |
On 1/7/2024 1:10 AM, Bonita Montero wrote: > Am 06.01.2024 um 22:15 schrieb Chris M. Thomasson: > >> Fwiw, some people were complaining about bad performance using >> hyperthreading. Turning it off in bios improved performance. >> Hence the paper was written to show them how to vastly improve >> performance when hyperthreading was turned on. You call it nerd >> stuff, and I still cannot figure out why? > > We were talking about mutual cache flushing and you don't kow > that this was the issue with switching of hyperthreading. > > I know that they had a problem and the provided workaround from Intel really did help out. I find it amusing that you are trying to tell me that this is all nerd stuff, as if it does not mean anything. Oh well.
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| From | Bonita Montero <Bonita.Montero@gmail.com> |
|---|---|
| Date | 2024-01-08 06:48 +0100 |
| Message-ID | <ung2bt$1eihc$1@raubtier-asyl.eternal-september.org> |
| In reply to | #118206 |
Am 07.01.2024 um 21:46 schrieb Chris M. Thomasson: > I know that they had a problem and the provided workaround from Intel > really did help out. ... Absolutely not, not with four way associativity.
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| From | "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> |
|---|---|
| Date | 2024-01-08 12:18 -0800 |
| Message-ID | <unhlaq$1lj9s$2@dont-email.me> |
| In reply to | #118207 |
On 1/7/2024 9:48 PM, Bonita Montero wrote: > Am 07.01.2024 um 21:46 schrieb Chris M. Thomasson: > >> I know that they had a problem and the provided workaround from Intel >> really did help out. ... > > Absolutely not, not with four way associativity. > Whatever you say; Sigh. I am done with this.
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| From | red floyd <no.spam.here@its.invalid> |
|---|---|
| Date | 2024-01-08 17:14 -0800 |
| Message-ID | <uni6mg$1ns04$1@redfloyd.dont-email.me> |
| In reply to | #118208 |
On 1/8/2024 12:18 PM, Chris M. Thomasson wrote: > On 1/7/2024 9:48 PM, Bonita Montero wrote: >> Am 07.01.2024 um 21:46 schrieb Chris M. Thomasson: >> >>> I know that they had a problem and the provided workaround from Intel >>> really did help out. ... >> >> Absolutely not, not with four way associativity. >> > > Whatever you say; Sigh. I am done with this. Intel just needs to call Bonita whenever they have an issue.
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