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Groups > comp.arch > #111650 > unrolled thread
| Started by | quadibloc <quadibloc@gmail.com> |
|---|---|
| First post | 2025-05-19 19:15 +0000 |
| Last post | 2025-06-19 01:03 +0000 |
| Articles |
20 on this page of 1000+
— 49 participants
Thread has 1028 articles; only the first 1000 are indexed. |
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Thread has 1028 articles; showing the first 1000 in depth-first order. Use the flat group view to see the rest.
Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-05-19 19:15 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-05-19 21:26 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-05-21 15:07 +0000
Re: Why I've Dropped In David Chmelik <dchmelik@gmail.com> - 2025-05-22 06:51 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-05-22 17:42 +0000
Re: Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-05-22 18:03 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-05-23 12:37 +0000
Re: Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-05-23 13:24 +0000
Re: Why I've Dropped In John Savard <quadibloc@invalid.invalid> - 2025-07-26 05:57 +0000
Re: Why I've Dropped In John Savard <quadibloc@invalid.invalid> - 2025-07-26 06:14 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-10 21:45 +0000
Re: Why I've Dropped In BGB <cr88192@gmail.com> - 2025-06-10 22:45 -0500
Re: Why I've Dropped In John Savard <quadibloc@invalid.invalid> - 2025-08-01 04:42 +0000
Re: Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-08-01 05:03 +0000
Re: Why I've Dropped In BGB <cr88192@gmail.com> - 2025-08-01 18:07 -0500
Re: Why I've Dropped In MitchAlsup <user5857@newsgrouper.org.invalid> - 2025-08-27 01:01 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-11 17:19 +0000
Re: Why I've Dropped In "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2025-06-11 12:16 -0700
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-12 02:11 +0000
Re: Why I've Dropped In "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2025-06-12 11:48 -0700
Re: Why I've Dropped In "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2025-06-15 17:26 -0700
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-12 08:00 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-10 22:53 +0000
Re: Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-11 05:56 +0000
Re: Why I've Dropped In BGB <cr88192@gmail.com> - 2025-06-11 04:42 -0500
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-11 16:37 +0000
Re: Why I've Dropped In BGB <cr88192@gmail.com> - 2025-06-11 14:47 -0500
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-12 19:13 +0000
Re: Why I've Dropped In BGB <cr88192@gmail.com> - 2025-06-12 16:30 -0500
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-13 00:00 +0000
Re: Why I've Dropped In BGB <cr88192@gmail.com> - 2025-06-15 13:21 -0500
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-15 18:42 +0000
Re: Why I've Dropped In BGB <cr88192@gmail.com> - 2025-06-15 16:42 -0500
Re: Why I've Dropped In anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-11 16:51 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-11 19:08 +0000
Re: Why I've Dropped In EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-11 18:00 -0400
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-11 23:01 +0000
Re: Why I've Dropped In anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-12 08:38 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-12 18:44 +0000
Re: Why I've Dropped In anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-20 05:56 +0000
Re: Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-12 19:55 +0000
Re: Why I've Dropped In BGB <cr88192@gmail.com> - 2025-06-11 16:28 -0500
Re: Why I've Dropped In anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-12 07:05 +0000
Re: Why I've Dropped In BGB <cr88192@gmail.com> - 2025-06-12 15:27 -0500
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-20 15:30 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-20 15:59 +0000
Re: Why I've Dropped In moi <findlaybill@blueyonder.co.uk> - 2025-06-20 17:12 +0100
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-20 19:46 +0000
Re: Why I've Dropped In John Savard <quadibloc@invalid.invalid> - 2025-07-23 16:03 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-11 14:12 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-11 16:49 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-11 17:34 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-11 19:16 +0000
Re: Why I've Dropped In BGB <cr88192@gmail.com> - 2025-06-14 14:22 -0500
Re: Why I've Dropped In Stefan Monnier <monnier@iro.umontreal.ca> - 2025-06-16 12:17 -0400
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-17 01:07 +0000
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-16 18:26 -0700
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-17 17:45 +0000
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-17 11:09 -0700
Re: Why I've Dropped In Stefan Monnier <monnier@iro.umontreal.ca> - 2025-06-17 16:43 -0400
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-17 21:18 +0000
Re: Why I've Dropped In Stefan Monnier <monnier@iro.umontreal.ca> - 2025-06-17 18:14 -0400
Re: Why I've Dropped In anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-18 07:31 +0000
Re: Why I've Dropped In Stefan Monnier <monnier@iro.umontreal.ca> - 2025-06-18 11:50 -0400
Re: Why I've Dropped In anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-19 08:56 +0000
Re: Why I've Dropped In BGB <cr88192@gmail.com> - 2025-06-18 15:37 -0500
Re: Why I've Dropped In "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2025-06-18 00:47 -0700
Re: Why I've Dropped In Stefan Monnier <monnier@iro.umontreal.ca> - 2025-06-18 11:22 -0400
Re: Why I've Dropped In "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2025-06-19 21:45 -0700
Re: Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-11 17:05 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-12 15:00 +0000
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-12 08:44 -0700
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-13 03:09 +0000
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-12 20:36 -0700
Re: Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-13 06:03 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-13 11:14 +0000
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-13 08:23 -0700
Re: Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-13 17:40 +0000
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-13 10:57 -0700
Re: Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-13 18:11 +0000
Re: Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-06-13 18:18 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-13 18:42 +0000
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-14 20:31 -0700
Re: Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-06-15 15:55 +0000
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-13 11:55 -0700
Re: base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-15 17:15 +0000
Re: base and bounds, Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-15 12:17 -0700
Re: base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-15 19:44 +0000
Re: base and bounds, Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-15 20:09 +0000
Re: base and bounds, Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-15 21:02 -0700
Re: base and bounds, Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-16 14:37 +0000
Re: base and bounds, Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-16 07:55 -0700
Re: base and bounds, Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-16 17:42 +0000
Re: base and bounds, Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-16 10:56 -0700
Re: base and bounds, Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-16 21:52 +0000
Re: base and bounds, Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-16 15:04 -0700
Re: base and bounds, Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-06-16 18:11 +0000
Re: base and bounds, Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-06-16 14:25 +0000
Re: base and bounds, Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-16 14:45 +0000
Re: base and bounds, Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-15 14:39 -0700
Re: base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-16 02:33 +0000
Re: base and bounds, Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-06-16 14:22 +0000
Re: big pages, base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-16 16:42 +0000
Re: big pages, base and bounds, Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-06-16 16:52 +0000
Re: Why I've Dropped In Lars Poulsen <lars@cleo.beagle-ears.com> - 2025-06-13 19:49 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-13 18:37 +0000
Re: Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-06-13 21:09 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-13 20:27 +0000
Re: Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-14 10:48 +0000
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-14 09:45 -0700
Re: Why I've Dropped In EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-14 13:56 -0400
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-14 12:23 -0700
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-14 21:26 +0000
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-14 14:37 -0700
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-14 21:49 +0000
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-14 20:34 -0700
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-15 03:52 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-15 04:04 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-15 04:09 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-15 04:38 +0000
Re: Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-15 07:37 +0000
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-15 07:00 -0700
Re: swapping pain, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-15 17:39 +0000
Re: swapping pain, Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-15 12:23 -0700
Re: base hackery, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-15 17:22 +0000
Re: Why I've Dropped In EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-15 09:48 -0400
Re: Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-14 18:51 +0000
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-14 12:33 -0700
Re: Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-14 20:06 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-15 19:29 +0000
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-18 09:55 -0700
Re: more addressing, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-18 18:19 +0000
Re: more addressing, Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-18 12:07 -0700
Re: more addressing, Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-19 06:13 +0000
Re: more addressing, Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-18 23:39 -0700
Re: more addressing, Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-19 07:46 +0000
Re: Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-06-13 13:14 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-13 11:52 +0000
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-13 08:15 -0700
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-13 19:50 +0000
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-13 13:50 -0700
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-13 22:01 +0000
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-13 23:10 -0700
Re: Why I've Dropped In anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-14 09:26 +0000
Re: Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-14 10:44 +0000
Re: Why I've Dropped In anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-14 15:40 +0000
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-14 09:24 -0700
Re: Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-14 16:49 +0000
Re: Why I've Dropped In anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-14 16:39 +0000
Re: Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-06-15 01:07 +0000
Re: Why I've Dropped In anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-15 07:10 +0000
Re: Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-06-15 16:01 +0000
Re: Why I've Dropped In anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-15 16:53 +0000
Re: static linked libraries, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-15 17:54 +0000
Re: Why I've Dropped In Robert Swindells <rjs@fdy2.co.uk> - 2025-06-15 19:24 +0000
Re: Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-06-16 14:15 +0000
Re: static libraries, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-15 17:00 +0000
Re: Why I've Dropped In John Savard <quadibloc@invalid.invalid> - 2025-07-24 10:47 +0000
Re: Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-14 16:56 +0000
Re: Why I've Dropped In Lars Poulsen <lars@cleo.beagle-ears.com> - 2025-06-14 12:42 +0000
Re: Why I've Dropped In anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-14 15:53 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-14 17:02 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-14 21:19 +0000
Re: fitting programs in Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-14 22:12 +0000
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-14 20:51 -0700
Re: base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-15 18:08 +0000
Re: base and bounds, Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-15 12:38 -0700
Re: old and slow base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-15 20:20 +0000
Re: old and slow base and bounds, Why I've Dropped In Al Kossow <aek@bitsavers.org> - 2025-06-15 18:48 -0700
Re: old and slow base and bounds, Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-18 10:35 -0700
Re: old and slow base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-18 19:51 +0000
Re: old and slow base and bounds, Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-18 15:30 -0700
Re: old and slow base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-19 01:23 +0000
Re: old and slow base and bounds, Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-18 19:41 -0700
Re: old and slow base and bounds, Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-19 05:36 +0000
Re: old and slow base and bounds, Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-18 23:10 -0700
Re: old and slow base and bounds, Why I've Dropped In EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-19 09:35 -0400
Re: old and slow base and bounds, Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-19 15:11 +0000
Re: Fortran, old and slow base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-19 18:03 +0000
Re: old and slow base and bounds, Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-19 18:53 +0000
Re: old and slow base and bounds, Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-19 23:18 +0000
Re: old and slow base and bounds, Why I've Dropped In EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-20 15:13 -0400
Re: old and slow base and bounds, Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-20 20:35 +0000
Re: old and slow base and bounds, Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-20 21:27 +0000
Re: old and slow base and bounds, Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-20 21:09 +0000
Re: old and slow base and bounds, Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-20 21:48 +0000
Re: old and slow base and bounds, Why I've Dropped In EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-21 14:57 -0400
Re: old and slow base and bounds, Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-19 23:36 +0000
Re: old and slow base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-20 01:32 +0000
Re: old and slow base and bounds, Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-20 13:45 +0000
Re: old and slow base and bounds, Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-20 17:19 +0000
Re: old and slow base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-20 18:06 +0000
Re: old and slow base and bounds, Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-20 18:31 +0000
Re: old and slow base and bounds, Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-20 12:27 -0700
Re: emulation, old and slow base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-20 20:16 +0000
Re: emulation, old and slow base and bounds, Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-20 20:47 +0000
Re: old and slow base and bounds, Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-20 21:26 +0000
Re: old and slow base and bounds, Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-06-21 14:33 +0000
Re: old and slow base and bounds, Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-20 21:34 +0000
Re: old and slow base and bounds, Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-20 23:57 +0000
Re: old and slow base and bounds, Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-21 00:06 +0000
Re: old and slow base and bounds, Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-21 00:13 +0000
Re: old and slow base and bounds, Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-20 23:20 -0700
Re: old and slow base and bounds, Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-21 07:40 +0000
Killer Micros (was: old and slow base and bounds) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-21 09:56 +0000
Re: old and slow base and bounds, Why I've Dropped In antispam@fricas.org (Waldek Hebisch) - 2025-06-21 14:25 +0000
Re: old and slow base and bounds, Why I've Dropped In Stefan Monnier <monnier@iro.umontreal.ca> - 2025-06-21 11:39 -0400
Re: old and slow base and bounds, Why I've Dropped In Vir Campestris <vir.campestris@invalid.invalid> - 2025-06-21 16:50 +0100
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-21 17:59 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-21 18:26 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-21 19:37 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In Lars Poulsen <lars@cleo.beagle-ears.com> - 2025-06-21 20:27 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-21 20:31 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-21 20:36 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2025-06-21 14:27 -0700
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In Terje Mathisen <terje.mathisen@tmsw.no> - 2025-06-24 09:45 +0200
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-22 06:34 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In Andreas Eder <a_eder_muc@web.de> - 2025-06-22 11:52 +0200
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-22 00:55 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In Vir Campestris <vir.campestris@invalid.invalid> - 2025-07-01 14:22 +0100
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-07-01 17:39 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-07-01 18:00 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In antispam@fricas.org (Waldek Hebisch) - 2025-06-22 20:23 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In Lynn Wheeler <lynn@garlic.com> - 2025-06-22 12:15 -1000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-22 22:44 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-23 09:23 -0400
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-23 20:04 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-23 23:16 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In Al Kossow <aek@bitsavers.org> - 2025-06-23 17:02 -0700
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-24 00:25 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-24 00:53 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-24 02:49 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-24 06:21 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In Terje Mathisen <terje.mathisen@tmsw.no> - 2025-06-24 09:59 +0200
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-24 06:16 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In antispam@fricas.org (Waldek Hebisch) - 2025-06-24 14:12 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In Al Kossow <aek@bitsavers.org> - 2025-06-24 07:43 -0700
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-24 14:53 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-06-24 14:48 +0000
Re: mainframe vs mini, old and slow base and bounds, Why I've Dropped In EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-24 13:01 -0400
Re: old and slow base and bounds, Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-21 17:49 +0000
Re: old and slow base and bounds, Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-06-21 14:36 +0000
Re: old and slow base and bounds, Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-19 13:37 +0000
Re: old and slow base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-19 17:52 +0000
Re: old and slow base and bounds, Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-19 19:00 +0000
Re: old and slow base and bounds, Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-20 07:42 -0700
Re: cramming 24 bits of address into 16 bits, was old and slow base and bounds John Levine <johnl@taugh.com> - 2025-06-20 18:40 +0000
Re: cramming 24 bits of address into 16 bits, was old and slow base and bounds EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-20 17:15 -0400
Re: cramming 24 bits of address into 16 bits, was old and slow base and bounds Thomas Koenig <tkoenig@netcologne.de> - 2025-06-20 21:30 +0000
Re: cramming 24 bits of address into 16 bits, was old and slow base and bounds John Levine <johnl@taugh.com> - 2025-06-21 17:21 +0000
Re: cramming 24 bits of address into 16 bits, was old and slow base and bounds EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-21 15:46 -0400
Re: cramming 24 bits of address into 16 bits, was old and slow base and bounds Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-21 22:42 -0700
Re: cramming 24 bits of address into 16 bits, was old and slow base and bounds Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-24 10:58 -0700
Re: cramming 24 bits of address into 16 bits, was old and slow base and bounds John Levine <johnl@taugh.com> - 2025-06-24 19:31 +0000
Re: old and slow base and bounds, Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-19 12:36 -0700
Re: old and slow base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-19 21:45 +0000
Re: old and slow base and bounds, Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-19 16:05 -0700
Re: old and slow base and bounds, Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-19 23:45 +0000
Re: old and slow base and bounds, Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-20 14:51 +0000
Re: old and slow base and bounds, Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-20 15:55 +0000
Re: old and slow base and bounds, Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-19 20:25 +0000
Re: old and slow base and bounds, Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-19 12:12 +0000
Re: old and slow base and bounds, Why I've Dropped In EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-19 10:32 -0400
Re: old and slow base and bounds, Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-19 14:54 +0000
Re: old and slow base and bounds, Why I've Dropped In EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-19 20:36 -0400
Re: old and slow base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-20 01:10 +0000
Re: old and slow base and bounds, Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-20 01:15 +0000
Re: old and slow base and bounds, Why I've Dropped In antispam@fricas.org (Waldek Hebisch) - 2025-06-21 12:04 +0000
Re: old and slow base and bounds, Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-21 20:32 +0000
Re: old and slow base and bounds, Why I've Dropped In antispam@fricas.org (Waldek Hebisch) - 2025-06-22 01:26 +0000
Re: old and slow base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-22 01:36 +0000
Re: old and slow base and bounds, Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-22 08:57 +0000
Re: linking and sortiing, old and slow base and bounds, John Levine <johnl@taugh.com> - 2025-06-22 17:52 +0000
Re: linking and sortiing, old and slow base and bounds, mitchalsup@aol.com (MitchAlsup1) - 2025-06-22 18:25 +0000
Re: linking and sortiing, old and slow base and bounds, scott@slp53.sl.home (Scott Lurndal) - 2025-06-22 20:29 +0000
Re: tape hacks, linking and sortiing John Levine <johnl@taugh.com> - 2025-06-22 22:44 +0000
Re: linking and sortiing, old and slow base and bounds, Thomas Koenig <tkoenig@netcologne.de> - 2025-06-23 06:07 +0000
Re: linking and sortiing, old and slow base and bounds, quadibloc <quadibloc@gmail.com> - 2025-06-23 09:56 +0000
Re: linking and sortiing, old and slow base and bounds, quadibloc <quadibloc@gmail.com> - 2025-06-23 10:01 +0000
Re: linking and sortiing, old and slow base and bounds, Thomas Koenig <tkoenig@netcologne.de> - 2025-06-23 17:13 +0000
Re: old and slow base and bounds, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-22 01:31 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-14 17:00 +0000
Re: Why I've Dropped In John Savard <quadibloc@invalid.invalid> - 2025-07-28 23:18 +0000
Re: Why I've Dropped In BGB <cr88192@gmail.com> - 2025-07-28 22:56 -0500
Re: Why I've Dropped In MitchAlsup <user5857@newsgrouper.org.invalid> - 2025-08-26 21:46 +0000
VAX (was: Why I've Dropped In) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-07-29 08:45 +0000
Re: VAX (was: Why I've Dropped In) John Levine <johnl@taugh.com> - 2025-07-29 16:44 +0000
Re: VAX (was: Why I've Dropped In) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-07-30 05:59 +0000
Re: VAX BGB <cr88192@gmail.com> - 2025-07-30 04:02 -0500
Re: VAX Thomas Koenig <tkoenig@netcologne.de> - 2025-07-30 16:24 +0000
Re: VAX BGB <cr88192@gmail.com> - 2025-07-30 13:24 -0500
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-01 17:02 +0000
Re: VAX BGB <cr88192@gmail.com> - 2025-08-01 15:24 -0500
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-02 15:33 +0000
Re: VAX BGB <cr88192@gmail.com> - 2025-08-02 15:15 -0500
Re: VAX BGB <cr88192@gmail.com> - 2025-08-02 18:55 -0500
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-04 16:33 +0000
Re: VAX MitchAlsup <user5857@newsgrouper.org.invalid> - 2025-08-25 00:56 +0000
Re: VAX MitchAlsup <user5857@newsgrouper.org.invalid> - 2025-08-31 18:04 +0000
What is more important MitchAlsup <user5857@newsgrouper.org.invalid> - 2025-09-04 15:23 +0000
Re: What is more important Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-09-04 10:25 -0700
Re: What is more important MitchAlsup <user5857@newsgrouper.org.invalid> - 2025-09-04 21:00 +0000
Re: What is more important BGB <cr88192@gmail.com> - 2025-09-04 16:54 -0500
Re: What is more important anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-09-05 15:03 +0000
Re: What is more important BGB <cr88192@gmail.com> - 2025-09-05 14:26 -0500
Re: What is more important BGB <cr88192@gmail.com> - 2025-09-05 14:38 -0500
Re: What is more important Robert Finch <robfi680@gmail.com> - 2025-09-05 21:56 -0400
Re: What is more important Thomas Koenig <tkoenig@netcologne.de> - 2025-09-10 13:31 +0000
Re: VAX (was: Why I've Dropped In) Lars Poulsen <lars@cleo.beagle-ears.com> - 2025-07-30 17:17 +0000
Re: VAX (was: Why I've Dropped In) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-01 17:16 +0000
Re: VAX (was: Why I've Dropped In) scott@slp53.sl.home (Scott Lurndal) - 2025-08-01 18:11 +0000
Re: VAX (was: Why I've Dropped In) cross@spitfire.i.gajendra.net (Dan Cross) - 2025-08-01 20:41 +0000
Re: VAX (was: Why I've Dropped In) Thomas Koenig <tkoenig@netcologne.de> - 2025-08-02 09:07 +0000
Re: VAX (was: Why I've Dropped In) Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-02 23:21 +0000
Re: VAX Stefan Monnier <monnier@iro.umontreal.ca> - 2025-08-02 23:10 -0400
Re: VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-03 09:14 +0000
Re: VAX Peter Flass <Peter@Iron-Spring.com> - 2025-08-03 07:41 -0700
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-06 10:24 +0000
Re: VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-06 23:40 +0000
Re: VAX John Ames <commodorejohn@gmail.com> - 2025-08-04 08:32 -0700
Re: VAX BGB <cr88192@gmail.com> - 2025-08-04 11:47 -0500
Re: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-08-04 17:20 +0000
Re: 32 vs 64 bits, was VAX John Levine <johnl@taugh.com> - 2025-08-04 18:17 +0000
Re: 32 vs 64 bits, was VAX Michael S <already5chosen@yahoo.com> - 2025-08-04 22:17 +0300
Re: 32 vs 64 bits, was VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-05 01:36 +0000
Re: 32 vs 64 bits, was VAX Thomas Koenig <tkoenig@netcologne.de> - 2025-08-04 20:00 +0000
Re: IBM's 32 vs 64 bits, was VAX John Levine <johnl@taugh.com> - 2025-08-04 21:04 +0000
Re: IBM's 32 vs 64 bits, was VAX Lynn Wheeler <lynn@garlic.com> - 2025-08-07 07:32 -1000
Re: VAX Stefan Monnier <monnier@iro.umontreal.ca> - 2025-08-04 15:40 -0400
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-06 16:34 +0000
Re: VAX Stefan Monnier <monnier@iro.umontreal.ca> - 2025-08-31 16:43 -0400
Re: VAX Lawrence D’Oliveiro <ldo@nz.invalid> - 2025-08-31 22:26 +0000
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-09-01 06:07 +0000
Re: VAX Lawrence D’Oliveiro <ldo@nz.invalid> - 2025-09-01 06:57 +0000
Debian on AMD64 (was: VAX) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-09-01 07:40 +0000
Re: Debian on AMD64 Stefan Monnier <monnier@iro.umontreal.ca> - 2025-09-01 12:15 -0400
Re: Debian on AMD64 BGB <cr88192@gmail.com> - 2025-09-01 11:33 -0500
Re: Debian on AMD64 anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-09-01 20:34 +0000
Re: VAX Marco Moock <mm@dorfdsl.de> - 2025-09-21 16:20 +0200
Re: VAX Nuno Silva <nunojsilva@invalid.invalid> - 2025-09-21 15:45 +0100
Re: VAX Michael S <already5chosen@yahoo.com> - 2025-09-21 17:54 +0300
Re: VAX Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-08-04 14:06 -0700
Re: VAX Michael S <already5chosen@yahoo.com> - 2025-08-05 00:21 +0300
Re: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-08-04 21:51 +0000
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-08-04 23:38 +0000
Re: VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-05 01:39 +0000
Re: VAX "Kerr-Mudd, John" <admin@127.0.0.1> - 2025-08-05 09:25 +0100
Re: VAX Terje Mathisen <terje.mathisen@tmsw.no> - 2025-08-05 17:24 +0200
Re: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-08-05 15:41 +0000
System calls (was: VAX) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-13 07:32 +0000
Re: System calls (was: VAX) scott@slp53.sl.home (Scott Lurndal) - 2025-08-13 15:03 +0000
Re: System calls (was: VAX) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-13 16:10 +0000
Re: System calls (was: VAX) scott@slp53.sl.home (Scott Lurndal) - 2025-08-13 18:15 +0000
Re: System calls (was: VAX) cross@spitfire.i.gajendra.net (Dan Cross) - 2025-08-13 19:40 +0000
Re: System calls (was: VAX) cross@spitfire.i.gajendra.net (Dan Cross) - 2025-08-13 19:25 +0000
Re: System calls (was: VAX) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-13 21:23 +0000
Re: System calls (was: VAX) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-14 07:58 +0000
Re: System calls (was: VAX) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-14 13:28 +0000
Re: System calls (was: VAX) cross@spitfire.i.gajendra.net (Dan Cross) - 2025-08-14 15:14 +0000
Re: System calls (was: VAX) cross@spitfire.i.gajendra.net (Dan Cross) - 2025-08-14 15:25 +0000
Re: System calls (was: VAX) scott@slp53.sl.home (Scott Lurndal) - 2025-08-14 15:32 +0000
Re: System calls (was: VAX) cross@spitfire.i.gajendra.net (Dan Cross) - 2025-08-14 15:44 +0000
Re: System calls David Brown <david.brown@hesbynett.no> - 2025-08-14 19:15 +0200
Re: System calls Thomas Koenig <tkoenig@netcologne.de> - 2025-08-14 17:43 +0000
Re: System calls David Brown <david.brown@hesbynett.no> - 2025-08-15 17:49 +0200
Re: System calls cross@spitfire.i.gajendra.net (Dan Cross) - 2025-08-14 21:44 +0000
Re: System calls David Brown <david.brown@hesbynett.no> - 2025-08-15 17:49 +0200
Re: System calls cross@spitfire.i.gajendra.net (Dan Cross) - 2025-08-15 18:33 +0000
Re: System calls (was: VAX) cross@spitfire.i.gajendra.net (Dan Cross) - 2025-08-13 18:51 +0000
Re: System calls (was: VAX) scott@slp53.sl.home (Scott Lurndal) - 2025-08-13 20:28 +0000
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-08-13 19:35 +0000
Re: VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-06 00:49 +0000
Re: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-08-06 13:48 +0000
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-08-04 23:24 +0000
Re: VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-05 01:41 +0000
Re: VAX vallor <vallor@cultnix.org> - 2025-08-05 05:56 +0000
Re: VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-05 01:34 +0000
Re: VAX Peter Flass <Peter@Iron-Spring.com> - 2025-08-01 20:06 -0700
Re: VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-02 03:37 +0000
Re: VAX ted@loft.tnolan.com (Ted Nolan <tednolan>) - 2025-08-02 04:14 +0000
Re: VAX "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2025-08-01 21:35 -0700
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-08-02 08:07 +0000
Re: VAX Al Kossow <aek@bitsavers.org> - 2025-08-02 01:48 -0700
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-08-04 23:45 +0000
Re: VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-02 23:08 +0000
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-03 16:51 +0000
Re: VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-04 00:04 +0000
Re: VAX BGB <cr88192@gmail.com> - 2025-08-03 21:07 -0500
Re: VAX Peter Flass <Peter@Iron-Spring.com> - 2025-08-03 20:39 -0700
Re: VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-04 04:50 +0000
Re: VAX Michael S <already5chosen@yahoo.com> - 2025-08-04 12:35 +0300
Re: VAX BGB <cr88192@gmail.com> - 2025-08-04 11:59 -0500
Re: VAX Michael S <already5chosen@yahoo.com> - 2025-08-04 12:19 +0300
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-04 12:09 +0000
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-04 14:51 +0000
Re: VAX Michael S <already5chosen@yahoo.com> - 2025-08-04 18:28 +0300
Re: VAX Keith Thompson <Keith.S.Thompson+u@gmail.com> - 2025-08-04 09:53 -0700
Re: VAX Thomas Koenig <tkoenig@netcologne.de> - 2025-08-04 16:58 +0000
Re: VAX "Brian G. Lucas" <bagel99@gmail.com> - 2025-08-05 13:03 -0500
Re: VAX Michael S <already5chosen@yahoo.com> - 2025-08-04 22:03 +0300
Re: VAX James Kuyper <jameskuyper@alumni.caltech.edu> - 2025-08-04 15:25 -0400
Re: VAX Michael S <already5chosen@yahoo.com> - 2025-08-04 22:40 +0300
Re: VAX "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2025-08-04 12:44 -0700
Re: VAX Keith Thompson <Keith.S.Thompson+u@gmail.com> - 2025-08-04 22:21 -0700
Re: VAX Kaz Kylheku <643-408-1753@kylheku.com> - 2025-08-05 21:25 +0000
Re: VAX Keith Thompson <Keith.S.Thompson+u@gmail.com> - 2025-08-05 19:14 -0700
Re: VAX Kaz Kylheku <643-408-1753@kylheku.com> - 2025-08-06 04:31 +0000
Re: VAX Michael S <already5chosen@yahoo.com> - 2025-08-06 11:48 +0300
Re: VAX James Kuyper <jameskuyper@alumni.caltech.edu> - 2025-08-06 11:56 -0400
Re: VAX Kaz Kylheku <643-408-1753@kylheku.com> - 2025-08-05 21:13 +0000
Re: VAX James Kuyper <jameskuyper@alumni.caltech.edu> - 2025-08-06 11:54 -0400
Re: VAX Keith Thompson <Keith.S.Thompson+u@gmail.com> - 2025-08-06 13:58 -0700
Re: VAX Kaz Kylheku <643-408-1753@kylheku.com> - 2025-08-05 21:08 +0000
Re: VAX Jakob Bohm <egenagwemdimtapsar@jbohm.dk> - 2025-08-17 20:18 +0200
Re: VAX Keith Thompson <Keith.S.Thompson+u@gmail.com> - 2025-08-17 22:18 -0700
Re: VAX Richard Heathfield <rjh@cpax.org.uk> - 2025-08-18 08:02 +0100
Re: VAX David Brown <david.brown@hesbynett.no> - 2025-08-18 11:34 +0200
Re: VAX Keith Thompson <Keith.S.Thompson+u@gmail.com> - 2025-08-18 21:57 -0700
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-04 15:11 +0000
Re: VAX Michael S <already5chosen@yahoo.com> - 2025-08-04 19:00 +0300
Re: VAX Michael S <already5chosen@yahoo.com> - 2025-08-04 19:04 +0300
Re: VAX Terje Mathisen <terje.mathisen@tmsw.no> - 2025-08-04 22:49 +0200
Re: VAX Michael S <already5chosen@yahoo.com> - 2025-08-05 00:14 +0300
Re: VAX Michael S <already5chosen@yahoo.com> - 2025-08-05 01:43 +0300
Re: VAX Terje Mathisen <terje.mathisen@tmsw.no> - 2025-08-05 17:31 +0200
Re: VAX Michael S <already5chosen@yahoo.com> - 2025-08-05 19:49 +0300
Re: VAX Terje Mathisen <terje.mathisen@tmsw.no> - 2025-08-05 22:17 +0200
Re: VAX Michael S <already5chosen@yahoo.com> - 2025-08-06 00:21 +0300
Re: VAX Terje Mathisen <terje.mathisen@tmsw.no> - 2025-08-06 16:19 +0200
3-way long addition (was: VAX) Michael S <already5chosen@yahoo.com> - 2025-08-06 20:43 +0300
Re: 3-way long addition Terje Mathisen <terje.mathisen@tmsw.no> - 2025-08-07 15:15 +0200
3-way long addition (was: VAX) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-19 05:47 +0000
Re: 3-way long addition (was: VAX) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-19 07:09 +0000
Re: 3-way long addition Terje Mathisen <terje.mathisen@tmsw.no> - 2025-08-19 12:11 +0200
Re: 3-way long addition anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-19 17:43 +0000
Re: 3-way long addition (was: VAX) Michael S <already5chosen@yahoo.com> - 2025-08-19 17:20 +0300
Re: 3-way long addition (was: VAX) Michael S <already5chosen@yahoo.com> - 2025-08-19 17:24 +0300
Re: 3-way long addition (was: VAX) Michael S <already5chosen@yahoo.com> - 2025-08-19 23:03 +0300
Re: 3-way long addition Terje Mathisen <terje.mathisen@tmsw.no> - 2025-08-20 10:50 +0200
Re: 3-way long addition Michael S <already5chosen@yahoo.com> - 2025-08-20 14:16 +0300
Intel ADX (was: 3-way long addition) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-20 14:08 +0000
Re: VAX Michael S <already5chosen@yahoo.com> - 2025-08-04 18:25 +0300
Re: VAX BGB <cr88192@gmail.com> - 2025-08-04 12:56 -0500
Re: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-08-04 14:22 +0000
Re: VAX Terje Mathisen <terje.mathisen@tmsw.no> - 2025-08-04 16:46 +0200
Re: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-08-04 15:05 +0000
Re: VAX Michael S <already5chosen@yahoo.com> - 2025-08-04 18:07 +0300
Re: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-08-04 15:32 +0000
Re: VAX Stefan Monnier <monnier@iro.umontreal.ca> - 2025-08-04 15:09 -0400
Re: VAX Michael S <already5chosen@yahoo.com> - 2025-08-04 22:31 +0300
Re: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-08-04 20:29 +0000
Re: VAX Michael S <already5chosen@yahoo.com> - 2025-08-05 00:08 +0300
Re: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-08-04 21:23 +0000
Re: VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-05 06:46 +0000
Re: VAX BGB <cr88192@gmail.com> - 2025-08-05 03:14 -0500
Re: VAX Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-08-05 11:52 -0700
Re: VAX Thomas Koenig <tkoenig@netcologne.de> - 2025-08-06 05:37 +0000
Re: VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-06 06:20 +0000
Re: VAX BGB <cr88192@gmail.com> - 2025-08-04 12:12 -0500
I32LP64 vs. ILP64 (was: VAX) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-06 11:28 +0000
Re: I32LP64 vs. ILP64 antispam@fricas.org (Waldek Hebisch) - 2025-08-06 15:55 +0000
Re: I32LP64 vs. ILP64 BGB <cr88192@gmail.com> - 2025-08-06 12:47 -0500
Re: I32LP64 vs. ILP64 BGB <cr88192@gmail.com> - 2025-08-06 12:00 -0500
Re: I32LP64 vs. ILP64 (was: VAX) Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-06 23:34 +0000
Re: VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-05 05:38 +0000
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-06 11:05 +0000
Re: VAX BGB <cr88192@gmail.com> - 2025-08-06 12:12 -0500
Re: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-08-06 18:22 +0000
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-06 10:32 +0000
Re: 64 bits, was VAX John Levine <johnl@taugh.com> - 2025-08-06 17:25 +0000
Re: 64 bits, was VAX Peter Flass <Peter@Iron-Spring.com> - 2025-08-06 12:11 -0700
Re: individual 64 bits, was VAX John Levine <johnl@taugh.com> - 2025-08-06 19:50 +0000
Re: individual 64 bits, was VAX scott@slp53.sl.home (Scott Lurndal) - 2025-08-06 20:30 +0000
Re: 64 bits, was VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-06 23:36 +0000
Re: 64 bits, was VAX Terje Mathisen <terje.mathisen@tmsw.no> - 2025-08-07 15:44 +0200
Re: 64 bits, was VAX Peter Flass <Peter@Iron-Spring.com> - 2025-08-07 07:34 -0700
Re: 64 bits, S/360 was VAX John Levine <johnl@taugh.com> - 2025-08-07 20:54 +0000
Re: 64 bits, was VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-08 03:51 +0000
Bit addressing (was: 64 bits) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-07 14:57 +0000
Re: Bit addressing drb@ihatespam.msu.edu (Dennis Boone) - 2025-08-07 15:54 +0000
Re: Bit addressing Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-08-07 13:01 -0700
Re: Bit addressing (was: 64 bits) Al Kossow <aek@bitsavers.org> - 2025-08-07 13:34 -0700
Re: VAX Lars Poulsen <lars@cleo.beagle-ears.com> - 2025-08-06 23:12 +0000
Re: VAX John Levine <johnl@taugh.com> - 2025-08-06 23:15 +0000
Re: VAX Lars Poulsen <lars@cleo.beagle-ears.com> - 2025-08-06 23:32 +0000
Re: word lengths in C, was VAX John Levine <johnl@taugh.com> - 2025-08-07 02:56 +0000
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-07 11:21 +0000
Re: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-08-07 13:34 +0000
Re: VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-06 23:38 +0000
Re: VAX Michael S <already5chosen@yahoo.com> - 2025-08-04 12:42 +0300
Re: VAX Al Kossow <aek@bitsavers.org> - 2025-08-04 03:32 -0700
Re: VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-05 05:37 +0000
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-04 13:42 +0000
Re: VAX Andy Burns <usenet@andyburns.uk> - 2025-08-04 16:50 +0100
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-08-04 23:52 +0000
Re: VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-05 05:35 +0000
Re: VAX cross@spitfire.i.gajendra.net (Dan Cross) - 2025-08-05 01:31 +0000
Re: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-08-05 13:46 +0000
Re: VAX cross@spitfire.i.gajendra.net (Dan Cross) - 2025-08-05 17:21 +0000
ILP32 code on 64-bit substrate (was: VAX) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-12 15:28 +0000
Re: ILP32 code on 64-bit substrate (was: VAX) scott@slp53.sl.home (Scott Lurndal) - 2025-08-12 16:08 +0000
Re: ILP32 code on 64-bit substrate BGB <cr88192@gmail.com> - 2025-08-12 11:53 -0500
Re: ILP32 code on 64-bit substrate aph@littlepinkcloud.invalid - 2025-08-12 17:57 +0000
Re: ILP32 code on 64-bit substrate John Levine <johnl@taugh.com> - 2025-08-12 19:09 +0000
Re: ILP32 code on 64-bit substrate OrangeFish <OrangeFish@invalid.invalid> - 2025-08-15 11:42 -0400
Re: ILP32 code on 64-bit substrate anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-13 06:11 +0000
Re: ILP32 code on 64-bit substrate scott@slp53.sl.home (Scott Lurndal) - 2025-08-13 14:24 +0000
Re: ILP32 code on 64-bit substrate anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-13 18:13 +0000
Re: VAX (was: Why I've Dropped In) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-02 09:28 +0000
Re: VAX (was: Why I've Dropped In) Thomas Koenig <tkoenig@netcologne.de> - 2025-08-02 15:29 +0000
Re: VAX Peter Flass <Peter@Iron-Spring.com> - 2025-08-02 15:33 -0700
Re: VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-02 23:17 +0000
Re: VAX (was: Why I've Dropped In) Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-02 23:20 +0000
Re: VAX (was: Why I've Dropped In) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-04 17:23 +0000
Re: VAX (was: Why I've Dropped In) Thomas Koenig <tkoenig@netcologne.de> - 2025-08-04 18:16 +0000
Re: VAX EricP <ThatWouldBeTelling@thevillage.com> - 2025-08-04 14:39 -0400
Re: VAX Thomas Koenig <tkoenig@netcologne.de> - 2025-08-04 19:59 +0000
Re: VAX (was: Why I've Dropped In) scott@slp53.sl.home (Scott Lurndal) - 2025-08-04 18:59 +0000
Re: VAX (was: Why I've Dropped In) Michael S <already5chosen@yahoo.com> - 2025-08-04 22:12 +0300
Re: VAX (was: Why I've Dropped In) Thomas Koenig <tkoenig@netcologne.de> - 2025-08-04 20:13 +0000
Re: VAX (was: Why I've Dropped In) Michael S <already5chosen@yahoo.com> - 2025-08-04 23:54 +0300
Re: VAX (was: Why I've Dropped In) Al Kossow <aek@bitsavers.org> - 2025-08-04 14:41 -0700
Re: VAX BGB <cr88192@gmail.com> - 2025-08-04 17:18 -0500
Re: VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-05 01:53 +0000
Re: VAX "Brian G. Lucas" <bagel99@gmail.com> - 2025-08-05 13:04 -0500
O.T. Where is Mitch? Was: VAX Michael S <already5chosen@yahoo.com> - 2025-08-07 23:48 +0300
Re: O.T. Where is Mitch? Was: VAX "Brian G. Lucas" <bagel99@gmail.com> - 2025-08-07 16:01 -0500
Re: O.T. Where is Mitch? Was: VAX BGB <cr88192@gmail.com> - 2025-08-08 01:41 -0500
Re: O.T. Where is Mitch? Was: VAX Terje Mathisen <terje.mathisen@tmsw.no> - 2025-08-08 11:58 +0200
Re: O.T. Where is Mitch? Was: VAX Michael S <already5chosen@yahoo.com> - 2025-08-08 13:20 +0300
Re: O.T. Where is Mitch? Was: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-08-08 14:22 +0000
Re: O.T. Where is Mitch? Was: VAX Niklas Holsti <niklas.holsti@tidorum.invalid> - 2025-08-08 18:34 +0300
Re: O.T. Where is Mitch? Was: VAX George Neuner <gneuner2@comcast.net> - 2025-08-08 19:07 -0400
Re: VAX (was: Why I've Dropped In) Thomas Koenig <tkoenig@netcologne.de> - 2025-08-05 21:01 +0000
Re: VAX (was: Why I've Dropped In) Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-06 00:59 +0000
Re: VAX Peter Flass <Peter@Iron-Spring.com> - 2025-08-05 20:15 -0700
Re: VAX Thomas Koenig <tkoenig@netcologne.de> - 2025-08-06 05:50 +0000
Re: VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-06 07:28 +0000
Re: VAX cross@spitfire.i.gajendra.net (Dan Cross) - 2025-08-06 10:48 +0000
Re: VAX Thomas Koenig <tkoenig@netcologne.de> - 2025-08-06 16:35 +0000
Re: VAX cross@spitfire.i.gajendra.net (Dan Cross) - 2025-08-08 01:57 +0000
Re: VAX (was: Why I've Dropped In) John Ames <commodorejohn@gmail.com> - 2025-08-06 08:28 -0700
Re: VAX (was: Why I've Dropped In) Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-06 23:45 +0000
Re: VAX (was: Why I've Dropped In) Charlie Gibbs <cgibbs@kltpzyxm.invalid> - 2025-08-07 01:49 +0000
Re: VAX (was: Why I've Dropped In) John Ames <commodorejohn@gmail.com> - 2025-08-07 08:28 -0700
Re: VAX (was: Why I've Dropped In) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-13 09:37 +0000
Re: VAX (was: Why I've Dropped In) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-13 08:22 +0000
Re: VAX (was: Why I've Dropped In) scott@slp53.sl.home (Scott Lurndal) - 2025-08-13 14:26 +0000
Re: VAX (was: Why I've Dropped In) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-13 17:50 +0000
Re: VAX drb@ihatespam.msu.edu (Dennis Boone) - 2025-08-14 17:12 +0000
Re: VAX EricP <ThatWouldBeTelling@thevillage.com> - 2025-08-14 15:22 -0400
Re: VAX Al Kossow <aek@bitsavers.org> - 2025-08-14 12:59 -0700
Re: VAX (was: Why I've Dropped In) scott@slp53.sl.home (Scott Lurndal) - 2025-08-13 14:44 +0000
Re: VAX (was: Why I've Dropped In) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-13 17:46 +0000
Re: VAX (was: Why I've Dropped In) ted@loft.tnolan.com (Ted Nolan <tednolan>) - 2025-08-13 18:26 +0000
Re: VAX Peter Flass <Peter@Iron-Spring.com> - 2025-08-13 12:09 -0700
Re: VAX (was: Why I've Dropped In) Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-05 01:47 +0000
Re: VAX (was: Why I've Dropped In) scott@slp53.sl.home (Scott Lurndal) - 2025-08-05 13:58 +0000
Re: VAX (was: Why I've Dropped In) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-06 16:47 +0000
Re: VAX Peter Flass <Peter@Iron-Spring.com> - 2025-08-06 12:12 -0700
Re: VAX Charlie Gibbs <cgibbs@kltpzyxm.invalid> - 2025-08-07 01:36 +0000
Re: VAX (was: Why I've Dropped In) Thomas Koenig <tkoenig@netcologne.de> - 2025-08-07 05:29 +0000
Re: VAX Peter Flass <Peter@Iron-Spring.com> - 2025-08-07 07:26 -0700
Re: VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-08 03:57 +0000
Re: VAX Michael S <already5chosen@yahoo.com> - 2025-08-08 11:43 +0300
Re: VAX (was: Why I've Dropped In) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-06 14:00 +0000
Re: VAX (was: Why I've Dropped In) Al Kossow <aek@bitsavers.org> - 2025-08-06 10:20 -0700
Re: VAX (was: Why I've Dropped In) Robert Swindells <rjs@fdy2.co.uk> - 2025-08-06 22:30 +0000
Re: VAX EricP <ThatWouldBeTelling@thevillage.com> - 2025-08-06 20:21 -0400
Re: VAX Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-07 02:22 +0000
Re: VAX John Ames <commodorejohn@gmail.com> - 2025-08-07 08:38 -0700
Re: VAX Terje Mathisen <terje.mathisen@tmsw.no> - 2025-08-07 17:52 +0200
Re: VAX George Neuner <gneuner2@comcast.net> - 2025-08-07 21:53 -0400
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-08 06:16 +0000
Re: VAX George Neuner <gneuner2@comcast.net> - 2025-08-08 19:48 -0400
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-07 10:27 +0000
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-08-07 11:06 +0000
Re: VAX (was: Why I've Dropped In) Al Kossow <aek@bitsavers.org> - 2025-08-04 12:27 -0700
Re: VAX (was: Why I've Dropped In) Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-05 01:46 +0000
Re: VAX (was: Why I've Dropped In) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-06 16:21 +0000
Re: VAX (was: Why I've Dropped In) Lawrence D'Oliveiro <ldo@nz.invalid> - 2025-08-05 01:43 +0000
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-08-01 23:41 +0000
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-03 16:42 +0000
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-08-05 00:55 +0000
Re: VAX Thomas Koenig <tkoenig@netcologne.de> - 2025-08-05 05:44 +0000
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-12 15:02 +0000
Re: VAX EricP <ThatWouldBeTelling@thevillage.com> - 2025-08-13 14:40 -0400
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-08-15 03:20 +0000
Re: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-08-15 15:10 +0000
Re: VAX pages John Levine <johnl@taugh.com> - 2025-08-15 16:53 +0000
Re: VAX pages BGB <cr88192@gmail.com> - 2025-08-15 13:19 -0500
Re: VAX pages Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-08-15 12:03 -0700
Re: VAX pages scott@slp53.sl.home (Scott Lurndal) - 2025-08-15 19:19 +0000
Re: VAX and other pages John Levine <johnl@taugh.com> - 2025-08-15 20:40 +0000
Re: VAX and other pages anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-15 21:22 +0000
Re: VAX and other pages John Levine <johnl@taugh.com> - 2025-08-16 01:22 +0000
Re: VAX and other pages anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-16 05:09 +0000
Re: VAX and other pages Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-08-16 10:00 -0700
Re: VAX and other pages John Levine <johnl@taugh.com> - 2025-08-16 17:06 +0000
Re: VAX and other pages antispam@fricas.org (Waldek Hebisch) - 2025-08-20 01:49 +0000
Re: VAX and other pages John Levine <johnl@taugh.com> - 2025-08-20 02:49 +0000
Re: VAX pages BGB <cr88192@gmail.com> - 2025-08-16 03:17 -0500
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-07-31 04:26 +0000
Re: VAX John Levine <johnl@taugh.com> - 2025-07-31 16:05 +0000
Re: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-07-31 19:01 +0000
Re: VAX John Levine <johnl@taugh.com> - 2025-07-31 19:57 +0000
Re: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-07-31 21:24 +0000
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-08-01 02:18 +0000
Re: VAX encoding John Levine <johnl@taugh.com> - 2025-08-01 15:30 +0000
Re: VAX encoding antispam@fricas.org (Waldek Hebisch) - 2025-08-01 18:08 +0000
Re: VAX encoding scott@slp53.sl.home (Scott Lurndal) - 2025-08-01 18:33 +0000
Re: VAX encoding antispam@fricas.org (Waldek Hebisch) - 2025-08-01 21:24 +0000
Re: VAX encoding Thomas Koenig <tkoenig@netcologne.de> - 2025-08-01 19:13 +0000
Re: VAX encoding MitchAlsup <user5857@newsgrouper.org.invalid> - 2025-08-28 15:10 +0000
Re: VAX encoding EricP <ThatWouldBeTelling@thevillage.com> - 2025-08-29 10:34 -0400
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-02 09:02 +0000
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-08-05 01:43 +0000
Re: VAX Thomas Koenig <tkoenig@netcologne.de> - 2025-08-05 05:48 +0000
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-08-05 14:13 +0000
Re: VAX George Neuner <gneuner2@comcast.net> - 2025-08-05 17:41 -0400
Re: VAX EricP <ThatWouldBeTelling@thevillage.com> - 2025-08-06 10:23 -0400
Re: VAX George Neuner <gneuner2@comcast.net> - 2025-08-08 21:43 -0400
Re: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-08-05 13:56 +0000
Re: VAX cross@spitfire.i.gajendra.net (Dan Cross) - 2025-08-05 16:44 +0000
Re: VAX Thomas Koenig <tkoenig@netcologne.de> - 2025-08-06 05:53 +0000
Re: VAX cross@spitfire.i.gajendra.net (Dan Cross) - 2025-08-06 11:10 +0000
Re: VAX Thomas Koenig <tkoenig@netcologne.de> - 2025-08-06 20:06 +0000
Re: VAX EricP <ThatWouldBeTelling@thevillage.com> - 2025-08-06 17:00 -0400
Re: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-08-06 21:14 +0000
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-07 11:59 +0000
Re: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-08-07 15:03 +0000
Re: VAX EricP <ThatWouldBeTelling@thevillage.com> - 2025-08-06 17:57 -0400
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-08-07 11:29 +0000
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-07 11:38 +0000
Re: VAX BGB <cr88192@gmail.com> - 2025-08-16 15:26 -0500
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-17 06:16 +0000
Re: VAX BGB <cr88192@gmail.com> - 2025-08-17 11:29 -0500
Re: VAX EricP <ThatWouldBeTelling@thevillage.com> - 2025-08-17 10:00 -0400
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-17 15:21 +0000
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-17 19:10 +0000
Re: VAX BGB <cr88192@gmail.com> - 2025-08-17 15:08 -0500
Re: VAX EricP <ThatWouldBeTelling@thevillage.com> - 2025-08-18 11:03 -0400
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-18 15:35 +0000
Re: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-08-18 17:19 +0000
Re: VAX EricP <ThatWouldBeTelling@thevillage.com> - 2025-08-20 14:36 -0400
Re: VAX EricP <ThatWouldBeTelling@thevillage.com> - 2025-08-20 16:41 -0400
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-08-21 16:21 +0000
Re: VAX BGB <cr88192@gmail.com> - 2025-08-17 12:53 -0500
Re: VAX Robert Swindells <rjs@fdy2.co.uk> - 2025-08-06 23:43 +0000
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-07 10:47 +0000
Re: VAX EricP <ThatWouldBeTelling@thevillage.com> - 2025-08-08 10:08 -0400
Re: VAX Thomas Koenig <tkoenig@netcologne.de> - 2025-08-09 08:07 +0000
Re: VAX EricP <ThatWouldBeTelling@thevillage.com> - 2025-08-09 10:03 -0400
Re: VAX Thomas Koenig <tkoenig@netcologne.de> - 2025-08-09 20:54 +0000
Re: VAX Al Kossow <aek@bitsavers.org> - 2025-08-09 14:57 -0700
Re: VAX EricP <ThatWouldBeTelling@thevillage.com> - 2025-08-13 14:18 -0400
Re: VAX Thomas Koenig <tkoenig@netcologne.de> - 2025-08-13 20:23 +0000
Re: VAX EricP <ThatWouldBeTelling@thevillage.com> - 2025-08-17 13:35 -0400
Re: VAX BGB <cr88192@gmail.com> - 2025-08-17 18:56 -0500
Re: VAX EricP <ThatWouldBeTelling@thevillage.com> - 2025-08-20 19:17 -0400
Re: VAX BGB <cr88192@gmail.com> - 2025-08-20 23:50 -0500
Re: VAX EricP <ThatWouldBeTelling@thevillage.com> - 2025-08-06 20:41 -0400
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-08-07 11:16 +0000
Re: VAX cross@spitfire.i.gajendra.net (Dan Cross) - 2025-08-09 09:04 +0000
Re: VAX Thomas Koenig <tkoenig@netcologne.de> - 2025-08-09 10:00 +0000
Re: VAX cross@spitfire.i.gajendra.net (Dan Cross) - 2025-08-10 12:06 +0000
Re: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-08-10 15:18 +0000
Re: byte me, PDP-10 edition, was VAX John Levine <johnl@taugh.com> - 2025-08-10 19:55 +0000
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-11 08:17 +0000
Re: VAX scott@slp53.sl.home (Scott Lurndal) - 2025-08-11 14:51 +0000
Re: VAX Thomas Koenig <tkoenig@netcologne.de> - 2025-08-11 17:27 +0000
Re: VAX Thomas Koenig <tkoenig@netcologne.de> - 2025-08-10 21:01 +0000
Re: VAX cross@spitfire.i.gajendra.net (Dan Cross) - 2025-08-13 11:25 +0000
Re: VAX Thomas Koenig <tkoenig@netcologne.de> - 2025-08-15 05:07 +0000
Re: VAX cross@spitfire.i.gajendra.net (Dan Cross) - 2025-08-15 12:57 +0000
Re: VAX Robert Swindells <rjs@fdy2.co.uk> - 2025-08-15 13:36 +0000
Re: VAX Thomas Koenig <tkoenig@netcologne.de> - 2025-08-18 05:48 +0000
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-08-05 20:34 +0000
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-12 15:59 +0000
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-08-20 03:47 +0000
Re: VAX Thomas Koenig <tkoenig@netcologne.de> - 2025-08-21 19:26 +0000
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-08-22 16:36 +0000
Re: VAX Thomas Koenig <tkoenig@netcologne.de> - 2025-08-22 17:21 +0000
Re: VAX John Levine <johnl@taugh.com> - 2025-08-22 16:45 +0000
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-08-23 16:38 +0000
Re: 360/91, was VAX John Levine <johnl@taugh.com> - 2025-08-23 19:36 +0000
Re: VAX anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-01 17:25 +0000
Re: VAX MitchAlsup <user5857@newsgrouper.org.invalid> - 2025-08-27 00:56 +0000
Re: VAX antispam@fricas.org (Waldek Hebisch) - 2025-08-28 07:49 +0000
Re: VAX (was: Why I've Dropped In) MitchAlsup <user5857@newsgrouper.org.invalid> - 2025-08-27 00:35 +0000
Re: VAX (was: Why I've Dropped In) Thomas Koenig <tkoenig@netcologne.de> - 2025-08-27 05:12 +0000
Re: VAX EricP <ThatWouldBeTelling@thevillage.com> - 2025-08-27 10:56 -0400
Re: VAX EricP <ThatWouldBeTelling@thevillage.com> - 2025-08-28 13:39 -0400
Re: VAX (was: Why I've Dropped In) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-27 17:19 +0000
Re: Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-14 17:30 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-14 18:39 +0000
Re: Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-13 17:42 +0000
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-13 11:00 -0700
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-14 16:04 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-14 16:12 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-14 16:50 +0000
Re: base registers and addres size, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-14 22:02 +0000
Re: base registers and addres size, Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-14 22:58 +0000
Re: base registers and addres size, Why I've Dropped In John Levine <johnl@taugh.com> - 2025-06-15 01:08 +0000
Re: Why I've Dropped In Lynn Wheeler <lynn@garlic.com> - 2025-06-17 16:47 -1000
Re: Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-06-18 13:48 +0000
Re: Why I've Dropped In BGB <cr88192@gmail.com> - 2025-06-13 17:52 -0500
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-14 04:04 +0000
Re: Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-14 10:45 +0000
Re: Why I've Dropped In anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-11 17:33 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-11 18:14 +0000
Re: Why I've Dropped In "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2025-06-11 12:30 -0700
Re: Why I've Dropped In "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2025-06-11 12:31 -0700
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-12 02:17 +0000
Re: Why I've Dropped In "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2025-06-12 11:55 -0700
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-13 03:30 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-13 20:40 +0000
Re: Why I've Dropped In "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2025-06-15 16:56 -0700
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-11 21:26 +0000
Re: Why I've Dropped In anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-12 06:30 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-12 07:57 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-12 14:06 +0000
Re: Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-06-12 13:43 +0000
Re: Why I've Dropped In anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-13 07:31 +0000
Re: Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-06-13 14:48 +0000
Re: Why I've Dropped In anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-13 15:38 +0000
Re: Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-13 17:10 +0000
Re: Why I've Dropped In antispam@fricas.org (Waldek Hebisch) - 2025-06-17 11:44 +0000
Re: Why I've Dropped In David Brown <david.brown@hesbynett.no> - 2025-06-17 16:00 +0200
Code density (was: Why I've Dropped In) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-17 14:17 +0000
Re: Code density (was: Why I've Dropped In) scott@slp53.sl.home (Scott Lurndal) - 2025-06-17 15:11 +0000
Re: Code density mitchalsup@aol.com (MitchAlsup1) - 2025-06-17 18:01 +0000
Re: Code density EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-17 23:55 -0400
Re: Code density anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-18 06:22 +0000
Re: Code density EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-18 09:32 -0400
Re: Code density "Kerr-Mudd, John" <admin@127.0.0.1> - 2025-06-18 16:19 +0100
Re: Code density mitchalsup@aol.com (MitchAlsup1) - 2025-06-18 18:27 +0000
Re: Code density anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-19 09:21 +0000
Re: Code density EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-22 10:05 -0400
Re: Code density mitchalsup@aol.com (MitchAlsup1) - 2025-06-22 17:35 +0000
Re: Code density scott@slp53.sl.home (Scott Lurndal) - 2025-06-22 20:26 +0000
Re: Code density mitchalsup@aol.com (MitchAlsup1) - 2025-06-26 01:12 +0000
Re: Code density scott@slp53.sl.home (Scott Lurndal) - 2025-06-26 15:17 +0000
Re: Code density EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-27 07:48 -0400
Re: Code density EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-27 08:33 -0400
Re: Code density Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-27 22:41 -0700
Re: Code density Thomas Koenig <tkoenig@netcologne.de> - 2025-06-28 07:45 +0000
Re: Code density anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-28 11:11 +0000
Re: Code density Thomas Koenig <tkoenig@netcologne.de> - 2025-06-28 12:00 +0000
Re: Code density mitchalsup@aol.com (MitchAlsup1) - 2025-06-28 16:01 +0000
Re: Code density Thomas Koenig <tkoenig@netcologne.de> - 2025-06-29 14:54 +0000
Re: Code density Terje Mathisen <terje.mathisen@tmsw.no> - 2025-06-29 18:01 +0200
Re: Code density mitchalsup@aol.com (MitchAlsup1) - 2025-06-29 20:50 +0000
Re: Code density EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-29 13:21 -0400
Re: Code density Thomas Koenig <tkoenig@netcologne.de> - 2025-06-29 20:41 +0000
Re: Code density George Neuner <gneuner2@comcast.net> - 2025-06-28 08:05 -0400
Re: Code density "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2025-06-28 21:29 -0700
Re: Code density scott@slp53.sl.home (Scott Lurndal) - 2025-06-27 13:55 +0000
Re: Code density EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-27 15:09 -0400
Re: Code density scott@slp53.sl.home (Scott Lurndal) - 2025-06-27 21:01 +0000
Re: Code density Thomas Koenig <tkoenig@netcologne.de> - 2025-06-28 09:07 +0000
Re: Code density John Levine <johnl@taugh.com> - 2025-06-28 16:30 +0000
Re: errno, Code density John Levine <johnl@taugh.com> - 2025-06-27 21:44 +0000
Re: errno, Code density EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-29 14:02 -0400
Re: errno, Code density anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-30 06:21 +0000
Re: errno, Code density EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-30 12:51 -0400
Re: errno, Code density scott@slp53.sl.home (Scott Lurndal) - 2025-06-30 17:13 +0000
Re: errno, Code density Michael S <already5chosen@yahoo.com> - 2025-07-01 13:11 +0300
Re: errno, Code density scott@slp53.sl.home (Scott Lurndal) - 2025-07-01 13:18 +0000
Re: errno, Code density Michael S <already5chosen@yahoo.com> - 2025-07-01 16:21 +0300
Re: errno, Code density Michael S <already5chosen@yahoo.com> - 2025-07-01 16:28 +0300
Re: errno, Code density scott@slp53.sl.home (Scott Lurndal) - 2025-07-01 14:08 +0000
Re: errno, Code density EricP <ThatWouldBeTelling@thevillage.com> - 2025-07-01 11:09 -0400
Re: assemblers, errno, Code density John Levine <johnl@taugh.com> - 2025-07-01 17:41 +0000
Re: errno, Code density mitchalsup@aol.com (MitchAlsup1) - 2025-06-30 17:11 +0000
Re: errno, Code density EricP <ThatWouldBeTelling@thevillage.com> - 2025-07-02 08:06 -0400
Re: errno, Code density mitchalsup@aol.com (MitchAlsup1) - 2025-07-02 15:38 +0000
Re: errno, Code density Michael S <already5chosen@yahoo.com> - 2025-06-30 13:55 +0300
Re: Code density George Neuner <gneuner2@comcast.net> - 2025-06-28 07:02 -0400
Re: Code density anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-30 16:08 +0000
Re: Code density anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-07-01 16:08 +0000
Re: Code density mitchalsup@aol.com (MitchAlsup1) - 2025-07-01 20:03 +0000
Re: Code density scott@slp53.sl.home (Scott Lurndal) - 2025-07-01 21:07 +0000
Re: Code density mitchalsup@aol.com (MitchAlsup1) - 2025-07-01 23:20 +0000
Re: Code density John Levine <johnl@taugh.com> - 2025-07-02 17:14 +0000
Re: Code density EricP <ThatWouldBeTelling@thevillage.com> - 2025-07-02 15:38 -0400
Re: Code density EricP <ThatWouldBeTelling@thevillage.com> - 2025-07-03 08:41 -0400
Re: Code density mitchalsup@aol.com (MitchAlsup1) - 2025-07-16 01:18 +0000
Re: Code density EricP <ThatWouldBeTelling@thevillage.com> - 2025-07-18 13:23 -0400
Re: Code density mitchalsup@aol.com (MitchAlsup1) - 2025-07-18 19:54 +0000
Re: Code density EricP <ThatWouldBeTelling@thevillage.com> - 2025-07-20 13:05 -0400
Re: Code density anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-07-20 17:33 +0000
Re: Code density mitchalsup@aol.com (MitchAlsup1) - 2025-07-20 20:09 +0000
Re: compacting branches, was Code density John Levine <johnl@taugh.com> - 2025-07-21 09:01 +0000
Re: compacting branches, was Code density anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-07-21 12:33 +0000
Re: compacting branches, was Code density Terje Mathisen <terje.mathisen@tmsw.no> - 2025-07-21 17:01 +0200
Re: compacting branches, was Code density anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-07-21 15:26 +0000
Re: compacting branches, was Code density Terje Mathisen <terje.mathisen@tmsw.no> - 2025-07-21 18:06 +0200
Re: compacting branches, was Code density anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-07-21 17:26 +0000
Re: compacting branches, was Code density Terje Mathisen <terje.mathisen@tmsw.no> - 2025-07-21 19:31 +0200
Re: Code density EricP <ThatWouldBeTelling@thevillage.com> - 2025-07-21 10:50 -0400
Re: Code density anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-07-21 15:28 +0000
Re: Code density EricP <ThatWouldBeTelling@thevillage.com> - 2025-07-21 17:08 -0400
Re: Code density anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-07-02 05:25 +0000
Re: Code density mitchalsup@aol.com (MitchAlsup1) - 2025-07-01 21:49 +0000
Re: Code density scott@slp53.sl.home (Scott Lurndal) - 2025-07-01 23:26 +0000
Re: Code density mitchalsup@aol.com (MitchAlsup1) - 2025-07-02 00:04 +0000
Re: Code density anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-07-02 05:18 +0000
Re: Code density EricP <ThatWouldBeTelling@thevillage.com> - 2025-07-02 11:20 -0400
Re: Code density mitchalsup@aol.com (MitchAlsup1) - 2025-07-02 15:45 +0000
Re: Code density scott@slp53.sl.home (Scott Lurndal) - 2025-07-02 16:56 +0000
Re: Code density mitchalsup@aol.com (MitchAlsup1) - 2025-07-02 17:06 +0000
Re: Code density anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-18 06:26 +0000
Re: Code density BGB <cr88192@gmail.com> - 2025-07-01 01:16 -0500
Re: Code density anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-07-01 15:23 +0000
Re: Code density BGB <cr88192@gmail.com> - 2025-07-01 10:53 -0500
Re: Why I've Dropped In EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-11 14:56 -0400
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-11 19:37 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-12 19:01 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-13 20:12 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-13 20:50 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-11 21:17 +0000
Re: Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-06-11 21:35 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-11 23:13 +0000
Re: Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-06-12 13:41 +0000
Re: Why I've Dropped In EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-12 09:38 -0400
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-12 19:19 +0000
Re: Why I've Dropped In "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2025-06-12 12:25 -0700
Re: Why I've Dropped In "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2025-06-12 12:27 -0700
Re: Why I've Dropped In anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-13 07:03 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-13 20:01 +0000
Re: Why I've Dropped In Robert Finch <robfi680@gmail.com> - 2025-06-14 04:35 -0400
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-14 15:22 +0000
Re: Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-14 17:30 +0000
Re: Why I've Dropped In Terje Mathisen <terje.mathisen@tmsw.no> - 2025-06-20 17:11 +0200
Re: Why I've Dropped In Stefan Monnier <monnier@iro.umontreal.ca> - 2025-06-20 12:43 -0400
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-20 17:38 +0000
Re: Why I've Dropped In Stefan Monnier <monnier@iro.umontreal.ca> - 2025-06-20 13:48 -0400
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-20 20:46 +0000
Re: Why I've Dropped In Stefan Monnier <monnier@iro.umontreal.ca> - 2025-06-20 18:13 -0400
Re: Why I've Dropped In antispam@fricas.org (Waldek Hebisch) - 2025-06-21 01:48 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-21 02:51 +0000
Re: Why I've Dropped In Terje Mathisen <terje.mathisen@tmsw.no> - 2025-06-24 08:15 +0200
Re: Why I've Dropped In "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2025-06-12 12:06 -0700
Re: Why I've Dropped In EricP <ThatWouldBeTelling@thevillage.com> - 2025-06-12 09:12 -0400
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-12 18:55 +0000
Re: Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-12 20:50 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-11 15:29 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-11 17:22 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-23 03:43 +0000
The Third Wish quadibloc <quadibloc@gmail.com> - 2025-06-23 12:43 +0000
Re: The Third Wish quadibloc <quadibloc@gmail.com> - 2025-06-23 12:47 +0000
Re: The Third Wish quadibloc <quadibloc@gmail.com> - 2025-06-24 17:19 +0000
Re: The Third Wish mitchalsup@aol.com (MitchAlsup1) - 2025-06-24 21:57 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-06-25 07:31 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-06-27 05:28 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-02 05:16 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-02 07:04 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-03 05:52 +0000
Re: The Third Wish Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-07-02 22:57 -0700
Re: The Third Wish Thomas Koenig <tkoenig@netcologne.de> - 2025-07-03 06:59 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-03 09:43 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-03 11:24 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-03 11:35 +0000
Re: The Third Wish mitchalsup@aol.com (MitchAlsup1) - 2025-07-16 01:11 +0000
Re: The Third Wish mitchalsup@aol.com (MitchAlsup1) - 2025-07-16 01:08 +0000
Re: The Third Wish mitchalsup@aol.com (MitchAlsup1) - 2025-07-16 18:22 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-16 23:36 +0000
Re: The Third Wish mitchalsup@aol.com (MitchAlsup1) - 2025-07-16 23:58 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-17 03:42 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-17 04:01 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-17 04:10 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-17 04:24 +0000
Re: The Third Wish mitchalsup@aol.com (MitchAlsup1) - 2025-07-17 15:16 +0000
Register windows (was: The Third Wish) Stefan Monnier <monnier@iro.umontreal.ca> - 2025-07-17 12:20 -0400
Re: Register windows mitchalsup@aol.com (MitchAlsup1) - 2025-07-17 16:53 +0000
Re: Register windows (was: The Third Wish) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-07-17 17:38 +0000
Re: Register windows (was: The Third Wish) scott@slp53.sl.home (Scott Lurndal) - 2025-07-17 19:17 +0000
Re: Register windows mitchalsup@aol.com (MitchAlsup1) - 2025-07-17 19:38 +0000
Re: Register windows Stefan Monnier <monnier@iro.umontreal.ca> - 2025-07-17 16:18 -0400
Re: Register windows Niklas Holsti <niklas.holsti@tidorum.invalid> - 2025-07-18 18:11 +0300
Re: Register windows Stefan Monnier <monnier@iro.umontreal.ca> - 2025-07-18 11:29 -0400
Re: Register windows Niklas Holsti <niklas.holsti@tidorum.invalid> - 2025-07-18 23:17 +0300
Re: Register windows mitchalsup@aol.com (MitchAlsup1) - 2025-07-20 17:28 +0000
Re: Register windows George Neuner <gneuner2@comcast.net> - 2025-07-20 22:27 -0400
Re: Register windows Niklas Holsti <niklas.holsti@tidorum.invalid> - 2025-07-21 12:11 +0300
Re: Register windows John Savard <quadibloc@invalid.invalid> - 2025-07-21 15:42 +0000
Re: Register windows MitchAlsup <user5857@newsgrouper.org.invalid> - 2025-08-21 21:48 +0000
Re: Register windows Thomas Koenig <tkoenig@netcologne.de> - 2025-08-23 08:51 +0000
Re: Register windows Stefan Monnier <monnier@iro.umontreal.ca> - 2025-08-29 17:07 -0400
Re: Register windows BGB <cr88192@gmail.com> - 2025-08-30 01:47 -0500
Re: Register windows antispam@fricas.org (Waldek Hebisch) - 2025-08-30 15:36 +0000
Re: Register windows BGB <cr88192@gmail.com> - 2025-08-30 13:19 -0500
Re: Register windows Stefan Monnier <monnier@iro.umontreal.ca> - 2025-08-30 14:22 -0400
Re: Register windows BGB <cr88192@gmail.com> - 2025-08-30 13:46 -0500
Re: Register windows MitchAlsup <user5857@newsgrouper.org.invalid> - 2025-08-31 16:21 +0000
Re: Register windows Thomas Koenig <tkoenig@netcologne.de> - 2025-09-12 17:47 +0000
Re: Register windows MitchAlsup <user5857@newsgrouper.org.invalid> - 2025-09-12 19:02 +0000
Re: Register windows scott@slp53.sl.home (Scott Lurndal) - 2025-09-14 15:16 +0000
Re: Register windows anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-09-17 05:55 +0000
Re: Register windows scott@slp53.sl.home (Scott Lurndal) - 2025-09-17 13:58 +0000
Re: Register windows anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-08-31 05:36 +0000
Where's Ivan was Re: Register windows Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-07-20 22:27 -0700
Re: Where's Ivan was Re: Register windows John Savard <quadibloc@invalid.invalid> - 2025-07-21 15:45 +0000
Re: Where's Ivan was Re: Register windows Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-07-21 12:05 -0700
Re: Where's Ivan was Re: Register windows scott@slp53.sl.home (Scott Lurndal) - 2025-07-21 19:56 +0000
Re: Where's Ivan was Re: Register windows Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-07-21 22:02 -0700
Re: The Third Wish mitchalsup@aol.com (MitchAlsup1) - 2025-07-17 15:02 +0000
Re: The Third Wish mitchalsup@aol.com (MitchAlsup1) - 2025-07-17 14:59 +0000
Re: The Third Wish anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-07-17 16:28 +0000
Re: The Third Wish mitchalsup@aol.com (MitchAlsup1) - 2025-07-17 19:21 +0000
Re: The Third Wish EricP <ThatWouldBeTelling@thevillage.com> - 2025-07-18 12:29 -0400
Re: The Third Wish mitchalsup@aol.com (MitchAlsup1) - 2025-07-17 14:49 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-17 18:03 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-17 18:27 +0000
Re: The Third Wish mitchalsup@aol.com (MitchAlsup1) - 2025-07-17 20:04 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-17 21:00 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-17 21:26 +0000
Re: The Third Wish Thomas Koenig <tkoenig@netcologne.de> - 2025-07-18 19:47 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-19 02:51 +0000
Re: The Third Wish mitchalsup@aol.com (MitchAlsup1) - 2025-07-17 21:29 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-17 21:45 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-17 21:58 +0000
Re: The Third Wish antispam@fricas.org (Waldek Hebisch) - 2025-07-18 15:39 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-18 17:08 +0000
Re: The Third Wish mitchalsup@aol.com (MitchAlsup1) - 2025-07-18 19:38 +0000
Re: The Third Wish Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-07-17 12:20 -0700
Re: The Third Wish mitchalsup@aol.com (MitchAlsup1) - 2025-07-17 19:52 +0000
PRF size (was: The Third Wish) Stefan Monnier <monnier@iro.umontreal.ca> - 2025-07-17 16:34 -0400
Re: PRF size mitchalsup@aol.com (MitchAlsup1) - 2025-07-17 21:38 +0000
Re: PRF size EricP <ThatWouldBeTelling@thevillage.com> - 2025-07-20 11:47 -0400
Re: PRF size mitchalsup@aol.com (MitchAlsup1) - 2025-07-20 17:34 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-17 20:32 +0000
Re: The Third Wish Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-07-17 21:35 -0700
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-18 11:18 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-18 11:28 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-18 11:33 +0000
Re: The Third Wish mitchalsup@aol.com (MitchAlsup1) - 2025-07-18 15:12 +0000
Re: The Third Wish Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-07-18 08:46 -0700
Re: The Third Wish scott@slp53.sl.home (Scott Lurndal) - 2025-07-18 16:25 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-18 17:14 +0000
Re: The Third Wish mitchalsup@aol.com (MitchAlsup1) - 2025-07-18 19:39 +0000
Re: The Third Wish anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-07-18 16:24 +0000
Re: The Third Wish Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-07-18 11:40 -0700
Re: The Third Wish mitchalsup@aol.com (MitchAlsup1) - 2025-07-18 19:45 +0000
Re: The Third Wish EricP <ThatWouldBeTelling@thevillage.com> - 2025-07-18 14:07 -0400
Re: The Third Wish antispam@fricas.org (Waldek Hebisch) - 2025-07-18 16:10 +0000
Re: The Third Wish anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-07-17 17:06 +0000
Re: The Third Wish antispam@fricas.org (Waldek Hebisch) - 2025-07-18 16:37 +0000
Re: The Third Wish mitchalsup@aol.com (MitchAlsup1) - 2025-07-16 18:09 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-15 22:24 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-16 00:00 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-16 00:22 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-16 01:49 +0000
Re: The Third Wish Thomas Koenig <tkoenig@netcologne.de> - 2025-07-16 17:33 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-16 23:24 +0000
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-16 23:26 +0000
Re: The Third Wish mitchalsup@aol.com (MitchAlsup1) - 2025-07-16 18:06 +0000
Re: The Third Wish "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2025-07-16 14:55 -0700
Re: The Third Wish John Savard <quadibloc@invalid.invalid> - 2025-07-16 12:26 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-13 10:43 +0000
Re: Why I've Dropped In John Savard <quadibloc@invalid.invalid> - 2025-07-22 04:30 +0000
Re: Why I've Dropped In John Savard <quadibloc@invalid.invalid> - 2025-07-22 16:29 +0000
Satisfaction John Savard <quadibloc@invalid.invalid> - 2025-07-24 11:07 +0000
Re: Satisfaction John Savard <quadibloc@invalid.invalid> - 2025-07-24 16:45 +0000
Re: Satisfaction John Savard <quadibloc@invalid.invalid> - 2025-07-24 20:04 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-16 03:46 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-12 15:38 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-12 19:24 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-13 00:11 +0000
Re: Why I've Dropped In BGB <cr88192@gmail.com> - 2025-06-16 17:14 -0500
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-16 23:37 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-17 01:20 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-17 17:41 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-17 17:59 +0000
Re: Why I've Dropped In BGB <cr88192@gmail.com> - 2025-06-17 14:04 -0500
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-17 21:19 +0000
Re: Why I've Dropped In BGB <cr88192@gmail.com> - 2025-06-18 01:16 -0500
Re: Why I've Dropped In Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-06-17 23:35 -0700
Re: Why I've Dropped In BGB <cr88192@gmail.com> - 2025-06-18 02:10 -0500
Re: Why I've Dropped In antispam@fricas.org (Waldek Hebisch) - 2025-06-25 22:24 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-25 23:00 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-18 16:09 +0000
Re: Why I've Dropped In "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2025-06-17 12:45 -0700
Re: Why I've Dropped In John Savard <quadibloc@invalid.invalid> - 2025-08-01 04:31 +0000
Re: Why I've Dropped In Stefan Monnier <monnier@iro.umontreal.ca> - 2025-06-17 16:51 -0400
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-17 21:11 +0000
Re: Why I've Dropped In anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2025-06-18 06:58 +0000
Re: Why I've Dropped In antispam@fricas.org (Waldek Hebisch) - 2025-06-18 14:45 +0000
Re: Why I've Dropped In BGB <cr88192@gmail.com> - 2025-06-17 01:28 -0500
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-17 12:58 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-17 13:12 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-17 17:52 +0000
Re: Why I've Dropped In scott@slp53.sl.home (Scott Lurndal) - 2025-06-17 18:14 +0000
Re: Why I've Dropped In Thomas Koenig <tkoenig@netcologne.de> - 2025-06-18 14:10 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-18 15:14 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-18 18:16 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-18 22:00 +0000
Re: Why I've Dropped In quadibloc <quadibloc@gmail.com> - 2025-06-18 23:20 +0000
Re: Why I've Dropped In mitchalsup@aol.com (MitchAlsup1) - 2025-06-19 01:03 +0000
Page 44 of 50 — ← Prev page 1 … 42 43 [44] 45 46 … 50 Next page →
| From | Thomas Koenig <tkoenig@netcologne.de> |
|---|---|
| Date | 2025-07-03 06:59 +0000 |
| Subject | Re: The Third Wish |
| Message-ID | <10459op$1umc$1@dont-email.me> |
| In reply to | #112465 |
Stephen Fuld <sfuld@alumni.cmu.edu.invalid> schrieb: > On 7/2/2025 10:52 PM, John Savard wrote: >> I think it will look familiar, and will represent the absolute height of >> insanity, the temptation to add to Concertina II being too strong for me >> to resist. > > By my count, you have just under a "gazillion" instruction, instruction > formats, etc. :-) > > Have you figured out how much combinatorial logic and how many gate > delays it will take to decode all of them? That might help to limit your > "insanity". That is an excellent idea. John, if write down the Boolean equations or the truth tables for your instruction decoding, then try to simplify them with espresso or a tool which does multi-level logic optimization like Berkeley ABC, you will get a much better idea of how complicated your design actually is. ABC also does some delay calculations for you if you map your design to a library. Highly instructive. -- This USENET posting was made without artificial intelligence, artificial impertinence, artificial arrogance, artificial stupidity, artificial flavorings or artificial colorants.
[toc] | [prev] | [next] | [standalone]
| From | John Savard <quadibloc@invalid.invalid> |
|---|---|
| Date | 2025-07-03 09:43 +0000 |
| Subject | Re: The Third Wish |
| Message-ID | <1045jcq$3n4d$1@dont-email.me> |
| In reply to | #112466 |
On Thu, 03 Jul 2025 06:59:37 +0000, Thomas Koenig wrote: > Stephen Fuld <sfuld@alumni.cmu.edu.invalid> schrieb: >> By my count, you have just under a "gazillion" instruction, instruction >> formats, etc. :-) >> Have you figured out how much combinatorial logic and how many gate >> delays it will take to decode all of them? That might help to limit >> your "insanity". > That is an excellent idea. John, if write down the Boolean equations or > the truth tables for your instruction decoding, then try to simplify > them with espresso or a tool which does multi-level logic optimization > like Berkeley ABC, you will get a much better idea of how complicated > your design actually is. ABC also does some delay calculations for you > if you map your design to a library. Highly instructive. In any case, until sanity overtakes me, and I remove this new feature from the Concertina II design, I have modified it to add instructions which make use of the extended register banks. I mean, really: how can I possibly omit the most important attribute required to give this instruction format its rightful Itanium nature? John Savard
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| From | John Savard <quadibloc@invalid.invalid> |
|---|---|
| Date | 2025-07-03 11:24 +0000 |
| Subject | Re: The Third Wish |
| Message-ID | <1045p9f$4tbk$1@dont-email.me> |
| In reply to | #112468 |
On Thu, 03 Jul 2025 09:43:55 +0000, John Savard wrote: > In any case, until sanity overtakes me, and I remove this new feature > from the Concertina II design, I have modified it to add instructions > which make use of the extended register banks. I mean, really: how can I > possibly omit the most important attribute required to give this > instruction format its rightful Itanium nature? Also, this exercise had a useful consequence. Adding a new instruction format that made it easy to achieve code that can take advantage of nine-way superscalar operation led me to review what the rest of the instruction set was doing. A previous addition made ten-way superscalar operation possible, but without any explicit indication of parallelism to promote it. With 17-bit short instructions, fourteen-way superscalar operation can be called upon without an explicit indication of parallelism; with one, though, that drops to eleven-way. But the maximum of 14-way could only be called upon with 14-bit instructions in the case where the pairs of instructions, at least, had an explicit indication of parallelism. I had enough opcode space available so that I was able to improve this to also use 15-bit instructions, to at least make it slightly more likely that the full superscalar power potentially available in this design could be used. John Savard
[toc] | [prev] | [next] | [standalone]
| From | John Savard <quadibloc@invalid.invalid> |
|---|---|
| Date | 2025-07-03 11:35 +0000 |
| Subject | Re: The Third Wish |
| Message-ID | <1045pu5$542q$1@dont-email.me> |
| In reply to | #112469 |
Without an explicit indication of parallelism, the real theoretical maximum is sixteen-way, with 14-bit instructions in the case without headers, and there's nothing much I can do to improve the ease of access to that. John Savard
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| From | mitchalsup@aol.com (MitchAlsup1) |
|---|---|
| Date | 2025-07-16 01:11 +0000 |
| Subject | Re: The Third Wish |
| Message-ID | <7b8bc9a3ab0df1f084570cbf9667bdb5@www.novabbs.org> |
| In reply to | #112470 |
On Thu, 3 Jul 2025 11:35:33 +0000, John Savard wrote: > Without an explicit indication of parallelism, the real > theoretical maximum is sixteen-way, with 14-bit instructions > in the case without headers, and there's nothing much I can > do to improve the ease of access to that. As noted above, I am doing 16-way decode on variable length instructions with no marking bits. > John Savard
[toc] | [prev] | [next] | [standalone]
| From | mitchalsup@aol.com (MitchAlsup1) |
|---|---|
| Date | 2025-07-16 01:08 +0000 |
| Subject | Re: The Third Wish |
| Message-ID | <5a36f7fc7dcdb828256469ec1bac582a@www.novabbs.org> |
| In reply to | #112469 |
On Thu, 3 Jul 2025 11:24:31 +0000, John Savard wrote: > On Thu, 03 Jul 2025 09:43:55 +0000, John Savard wrote: > >> In any case, until sanity overtakes me, and I remove this new feature >> from the Concertina II design, I have modified it to add instructions >> which make use of the extended register banks. I mean, really: how can I >> possibly omit the most important attribute required to give this >> instruction format its rightful Itanium nature? > > Also, this exercise had a useful consequence. Adding a new instruction > format that made it easy to achieve code that can take advantage of > nine-way superscalar operation led me to review what the rest of the > instruction set was doing. > > A previous addition made ten-way superscalar operation possible, but > without any explicit indication of parallelism to promote it. > > With 17-bit short instructions, fourteen-way superscalar operation can > be called upon without an explicit indication of parallelism; with one, > though, that drops to eleven-way. We cannot believe that until you produce a compiler. OH and btw, I can achieve 16-way decode parallelism with a variable length encoding and nothing that marks any kind of instruction boundary--AND--I have compiler, linker, ... Nor do I have a zillion instructions, I only have 63 patterns to recognize. > But the maximum of 14-way could only be called upon with 14-bit > instructions in the case where the pairs of instructions, at least, > had an explicit indication of parallelism. I had enough opcode space > available so that I was able to improve this to also use 15-bit > instructions, to at least make it slightly more likely that the full > superscalar power potentially available in this design could be used. > > John Savard
[toc] | [prev] | [next] | [standalone]
| From | mitchalsup@aol.com (MitchAlsup1) |
|---|---|
| Date | 2025-07-16 18:22 +0000 |
| Subject | Re: The Third Wish |
| Message-ID | <603de20a27371d2fefb2e987a0c9ded6@www.novabbs.org> |
| In reply to | #112575 |
On Wed, 16 Jul 2025 1:08:19 +0000, MitchAlsup1 wrote: > On Thu, 3 Jul 2025 11:24:31 +0000, John Savard wrote: > >> On Thu, 03 Jul 2025 09:43:55 +0000, John Savard wrote: >> >>> In any case, until sanity overtakes me, and I remove this new feature >>> from the Concertina II design, I have modified it to add instructions >>> which make use of the extended register banks. I mean, really: how can I >>> possibly omit the most important attribute required to give this >>> instruction format its rightful Itanium nature? >> >> Also, this exercise had a useful consequence. Adding a new instruction >> format that made it easy to achieve code that can take advantage of >> nine-way superscalar operation led me to review what the rest of the >> instruction set was doing. >> >> A previous addition made ten-way superscalar operation possible, but >> without any explicit indication of parallelism to promote it. >> >> With 17-bit short instructions, fourteen-way superscalar operation can >> be called upon without an explicit indication of parallelism; with one, >> though, that drops to eleven-way. > > We cannot believe that until you produce a compiler. > > OH and btw, I can achieve 16-way decode parallelism with a variable > length encoding and nothing that marks any kind of instruction > boundary--AND--I have compiler, linker, ... > > Nor do I have a zillion instructions, I only have 63 patterns to > recognize. I should expand on this:: There are 4 groups of instructions where we use the top 2-bits of the major OpCode:: 00 OpCode extensions 01 Control transfer group 10 Memory reference with 16-bit displacement 11 Calculation with 16-bit immediate Of these:: 000 Predication and shifts of constant (saves imm16 space 12-bits imm) 001 is the only group that has variable length 010 is LOOP 011 is conventional branch 100 it LDs with disp16 101 is STs with disp16 110 is integer with imm16 111 is logical with imm16 All very RISC-like at this point. In the VLE group; Inst<15:13,11> provide all the bits for operand routing and for VLE instruction length--they are mashed up together to reduce entropy. >> But the maximum of 14-way could only be called upon with 14-bit >> instructions in the case where the pairs of instructions, at least, >> had an explicit indication of parallelism. I had enough opcode space >> available so that I was able to improve this to also use 15-bit >> instructions, to at least make it slightly more likely that the full >> superscalar power potentially available in this design could be used. >> >> John Savard
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| From | John Savard <quadibloc@invalid.invalid> |
|---|---|
| Date | 2025-07-16 23:36 +0000 |
| Subject | Re: The Third Wish |
| Message-ID | <1059d1b$vrmt$3@dont-email.me> |
| In reply to | #112575 |
On Wed, 16 Jul 2025 01:08:19 +0000, MitchAlsup1 wrote: > OH and btw, I can achieve 16-way decode parallelism with a variable > length encoding and nothing that marks any kind of instruction > boundary--AND--I have compiler, linker, ... > > Nor do I have a zillion instructions, I only have 63 patterns to > recognize. I certainly acknowledge that I'm not as good as you at this sort of thing. Theoretically, because the architecture involves separate banks of floating-point and integer registers, and there are both regular banks with 32 registers, and extended banks with 128 registers, and instruction formats that divide these registers into eight-register groups (sort of like a register window, but not quite)... if it weren't for the fact that I envisage only fetching 256 bits from memory in any given cycle (of course, within loops, one can get instructions from internal cache) this theoretically allows for 40-way superscalar operation. In practice, I doubt that anyone would write code, even carefully by hand, that would even manage 14-way superscalar operation for very long, so I admit it's unlikely to be terribly useful to include this in most implementations. The ISA is designed, though, so that (except for its immense bloat) it could be used in a special-purpose CPU without OoO that's designed for some kind of embedded use in, say, image processing or something where it could be given that kind of specialized code to run. A CPU designed instead for use in a desktop workstation would presumably have microarchitectural capabilities appropriate to that application. John Savard
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| From | mitchalsup@aol.com (MitchAlsup1) |
|---|---|
| Date | 2025-07-16 23:58 +0000 |
| Subject | Re: The Third Wish |
| Message-ID | <3978ba63d716259121cdc4fe54d87062@www.novabbs.org> |
| In reply to | #112594 |
On Wed, 16 Jul 2025 23:36:11 +0000, John Savard wrote: > On Wed, 16 Jul 2025 01:08:19 +0000, MitchAlsup1 wrote: > >> OH and btw, I can achieve 16-way decode parallelism with a variable >> length encoding and nothing that marks any kind of instruction >> boundary--AND--I have compiler, linker, ... >> >> Nor do I have a zillion instructions, I only have 63 patterns to >> recognize. > > I certainly acknowledge that I'm not as good as you at this sort > of thing. > > Theoretically, because the architecture involves separate banks of > floating-point and integer registers, and there are both regular banks > with 32 registers, and extended banks with 128 registers, and Point of order:: all register files that have the same width (64-bits) should be a single file. This makes varargs easier, allows using integer operations on FP operands (extract exponent, insert exponent, copysign) which are mandated by the standards. Either you have an integer set of registers and a FP set of registers and a nearly complete set of integer operations on FP registers, or you can dispense with the nonsense and have a single general purpose register file. I have evidence (data) indicating My 66000 with only 32-registers AND universal constants needs fewer registers than RISC-V with 32 integer and 32 FP registers on many applications, including those you think need 32+32. > instruction formats that divide these registers into eight-register > groups (sort of like a register window, but not quite)... if it weren't > for the fact that I envisage only fetching 256 bits from memory in any > given cycle (of course, within loops, one can get instructions from > internal cache) this theoretically allows for 40-way superscalar > operation. I have always been a cynic to this partition. > In practice, I doubt that anyone would write code, even carefully by > hand, that would even manage 14-way superscalar operation for very > long, so I admit it's unlikely to be terribly useful to include this in > most implementations. That is why VLIW is failing or has failed. > The ISA is designed, though, so that (except for its immense bloat) it > could be used in a special-purpose CPU without OoO that's designed for > some kind of embedded use in, say, image processing or something where > it could be given that kind of specialized code to run. LoL. > A CPU designed instead for use in a desktop workstation would presumably > have microarchitectural capabilities appropriate to that application. Like fast context switches, which multiple register files PREVENTS !! > John Savard
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| From | John Savard <quadibloc@invalid.invalid> |
|---|---|
| Date | 2025-07-17 03:42 +0000 |
| Subject | Re: The Third Wish |
| Message-ID | <1059reg$1652n$1@dont-email.me> |
| In reply to | #112595 |
On Wed, 16 Jul 2025 23:58:41 +0000, MitchAlsup1 wrote: > Point of order:: all register files that have the same width (64-bits) > should be a single file. This relates to a point that occurred to me. Many CISC microprocessors had register banks of eight registers. RISC had register banks of 32 registers, which they thought would avoid the need for OoO. Increasing performance demands, though, made that no longer true. Well, then, the extended register banks with 128 registers in them... are there to be used by programs intended to run on chips that don't have OoO. If an implementation does have OoO, nothing is to be gained by bothering with those registers (which still won't have rename registers associated with them, even in an OoO implementation; so OoO won't work on the parts of the program that use them). > Like fast context switches, which multiple register files PREVENTS !! You could have an operating system that neglects to save certain register files on interrupts, which means programs can't use them. (There's a precedent: the Commodore 64 didn't save the status bit for decimal mode, so user programs couldn't use that feature of the 6502.) John Savard
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| From | John Savard <quadibloc@invalid.invalid> |
|---|---|
| Date | 2025-07-17 04:01 +0000 |
| Subject | Re: The Third Wish |
| Message-ID | <1059sj8$16a8p$1@dont-email.me> |
| In reply to | #112597 |
On Thu, 17 Jul 2025 03:42:08 +0000, John Savard wrote: > On Wed, 16 Jul 2025 23:58:41 +0000, MitchAlsup1 wrote: > >> Point of order:: all register files that have the same width (64-bits) >> should be a single file. > > This relates to a point that occurred to me. > > Many CISC microprocessors had register banks of eight registers. > > RISC had register banks of 32 registers, which they thought would avoid > the need for OoO. Increasing performance demands, though, > made that no longer true. > > Well, then, the extended register banks with 128 registers in them... > > are there to be used by programs intended to run on chips that don't > have OoO. If an implementation does have OoO, nothing is to be gained by > bothering with those registers (which still won't have rename registers > associated with them, even in an OoO implementation; so OoO won't work > on the parts of the program that use them). And there are other things related to this that have occurred to me. You've used the term "GBOoO" - Great Big out-of-order - to describe the current offerings of companies like Intel and AMD. You hadn't formally defined the term, at least not in any post that I've noticed. For purposes of discussion below, I'm going to provide a definition which may not correspond to what you were intending. This definition is: In "normal" out-of-order, each register has three rename registers associated with it, for a total of 4. In "big" out-of-order, each register has fifteen rename registers associated with it, for a total of 16. In "great big" out of order, each register has sixty-three rename registers associated with it, for a total of 64. With this definition of the typical implementation in each size class of OoO, one can construct a mythical history of sorts. In "the beginning", CISC chips had normal OoO, and RISC chips did not have OoO. Since the CISC chips had register files of 8 registers, and the RISC chips had register files of 32 registers, the two were equivalent in performance. (Given cache misses, maybe the RISC chips still needed scoreboards.) And then the RISC chips got "normal" OoO, and to keep up, the CISC chips got "big" OoO. This is the stage we would be at when I say that in my design, the 32-register normal register banks would have OoO, but the 128-register extended register banks wouldn't. If things have progressed further, so that RISC chips have "big" OoO and CISC chips have "great big" OoO, by the definitions I've given above, then my design, to keep up, would have to provide "big" OoO for the normal register files, but only "normal" OoO for the extended register files. John Savard
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| From | John Savard <quadibloc@invalid.invalid> |
|---|---|
| Date | 2025-07-17 04:10 +0000 |
| Subject | Re: The Third Wish |
| Message-ID | <1059t3a$16euf$1@dont-email.me> |
| In reply to | #112598 |
On Thu, 17 Jul 2025 04:01:44 +0000, John Savard wrote: > If things have progressed further, so that RISC chips have "big" OoO and > CISC chips have "great big" OoO, by the definitions I've given above, > then my design, to keep up, would have to provide "big" OoO for the > normal register files, but only "normal" OoO for the extended register > files. I think that a clarification is in order here. I don't know, but I strongly suspect, that what you term "Great Big out of order" is what I've called just "big" out-of-order, and that this is already well past the point of diminishing returns. So that what I've called "great big" out of order is instead something so far past the point of sanity that I don't have to worry about it happening in real life. But I could be wrong. John Savard
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| From | John Savard <quadibloc@invalid.invalid> |
|---|---|
| Date | 2025-07-17 04:24 +0000 |
| Subject | Re: The Third Wish |
| Message-ID | <1059tti$16il5$1@dont-email.me> |
| In reply to | #112599 |
On Thu, 17 Jul 2025 04:10:18 +0000, John Savard wrote: > I think that a clarification is in order here. And, come to think of it, _another_ clarification may be needed. If a register file with "normal" out-of-order, three rename registers for each register, and 32 registers to a register bank, is "equivalent" in performance to a register file with 128 registers and no OoO support, then the latter provides no performance benefit, so what is it there for? Someone might ask that who wasn't following my discussion of the Concertina II design. So I think I had better re-iterate the point: What the 128-register extended register files are _for_ is to provide better performance on implementations that don't have OoO at all, for any of the registers. They're also present on implementations with OoO for *compatibility* reasons. This is what may not be clear to some. John Savard
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| From | mitchalsup@aol.com (MitchAlsup1) |
|---|---|
| Date | 2025-07-17 15:16 +0000 |
| Subject | Re: The Third Wish |
| Message-ID | <f19813b55e635188c81f989aa63f0462@www.novabbs.org> |
| In reply to | #112600 |
On Thu, 17 Jul 2025 4:24:18 +0000, John Savard wrote:
> On Thu, 17 Jul 2025 04:10:18 +0000, John Savard wrote:
>
>> I think that a clarification is in order here.
>
> And, come to think of it, _another_ clarification may be needed.
>
> If a register file with "normal" out-of-order, three rename
> registers for each register, and 32 registers to a register bank, is
>
> "equivalent" in performance to a register file with 128 registers and
> no OoO support,
>
> then the latter provides no performance benefit, so what is it there
> for?
That is NOT HOW ONE RENAMES !!!!!!!
One has a pool of rename registers. DECODE has a demand for rename
registers (Rd), and retire has a supply of rename registers (Write RD
into RF), and ANY rename register can stand in for ANY architectural
register. As long as the pool is not depleted, everything runs smoothly.
> Someone might ask that who wasn't following my discussion of the
> Concertina II design. So I think I had better re-iterate the point:
>
> What the 128-register extended register files are _for_ is to
> provide better performance on implementations that don't have OoO
> at all, for any of the registers. They're also present on
> implementations with OoO for *compatibility* reasons.
........... CPU time . Reg Access
.8 registers 1.30 .... 1/4
16 registers 1.15 .... 1/3
32 registers 1.00 .... 2/4
64 registers 0.97 .... 3/4
128 registers 0.96 .... 4/4
32 is the knee of the curve. HW always wants to operate at the knee
of the curve (Bill Moyer 1982). If you make the Register file as
big as the cache it will take just as long as the cache to access
(Andy Glew circa 1995).
The only good arguments I have heard wrt big architectural register
files has to do with things like Register-Windows and/or optimizing
CALL/RET interface.
BUT (the big but) adding cycles to the pipeline degrades performance
for ALL instructions, not just the ones that use registers 32..128 !!
{{like doubling the size of L2 and adding 1 cycle of added latency
ends up running slower 50% of the time--choose your L2 latency with
care (Przybylski).}}
> This is what may not be clear to some.
Some == You
> John Savard
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| From | Stefan Monnier <monnier@iro.umontreal.ca> |
|---|---|
| Date | 2025-07-17 12:20 -0400 |
| Subject | Register windows (was: The Third Wish) |
| Message-ID | <jwvldomkdua.fsf-monnier+comp.arch@gnu.org> |
| In reply to | #112608 |
> The only good arguments I have heard wrt big architectural register
> files has to do with things like Register-Windows and/or optimizing
> CALL/RET interface.
But even there, it justifies only additional "second-class registers",
i.e. where the set of immediately addressable registers can still be the
same size as usual (e.g. 16 or 32), but you can quickly push some of
those to some kind of "stack" and then pull them back in.
IIRC the Mill had actually 2 categories of "second-class registers":
the stack and the scratch registers.
I think you can get similar benefits with "cache-line sized" memory
operations that load/store several registers at a time (assuming you
have good enough store-to-load forwarding). Or even fold those
loads&stores into some kind of CALL/RET instructions, which can let you
start the control-flow part of the CALL before the stores, and similarly
start the loads before the control flow part of the RET is done.
Stefan
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| From | mitchalsup@aol.com (MitchAlsup1) |
|---|---|
| Date | 2025-07-17 16:53 +0000 |
| Subject | Re: Register windows |
| Message-ID | <62281f3a6bbbf6f152fb13bb66cc38cf@www.novabbs.org> |
| In reply to | #112609 |
On Thu, 17 Jul 2025 16:20:13 +0000, Stefan Monnier wrote: >> The only good arguments I have heard wrt big architectural register >> files has to do with things like Register-Windows and/or optimizing >> CALL/RET interface. > > But even there, it justifies only additional "second-class registers", > i.e. where the set of immediately addressable registers can still be the > same size as usual (e.g. 16 or 32), but you can quickly push some of > those to some kind of "stack" and then pull them back in. > IIRC the Mill had actually 2 categories of "second-class registers": > the stack and the scratch registers. > > I think you can get similar benefits with "cache-line sized" memory > operations that load/store several registers at a time (assuming you > have good enough store-to-load forwarding). Or even fold those > loads&stores into some kind of CALL/RET instructions, which can let you > start the control-flow part of the CALL before the stores, and similarly > start the loads before the control flow part of the RET is done. Yes, that is what we ended up doing in My 66000: ENTER saves the preserved registers (and generally Ret Address) EXIT restores the preserved registers and transfers control back ....to caller Both ENTER and EXIT can perform 1-32 reads/writes to sequential memory addresses and add/sub to SP and optionally setup FP. ENTER and EXIT are within the called subroutine. By using ENTER and EXIT, the preserved registers can be written to memory the normal LD/ST instructions have no access, so bad array indexes cannot harm the call/return contract, eliminating ROP attacks. I am happier with this than the register windows stuff I had to deal with in SPARC. > > > Stefan
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| From | anton@mips.complang.tuwien.ac.at (Anton Ertl) |
|---|---|
| Date | 2025-07-17 17:38 +0000 |
| Subject | Re: Register windows (was: The Third Wish) |
| Message-ID | <2025Jul17.193835@mips.complang.tuwien.ac.at> |
| In reply to | #112609 |
Stefan Monnier <monnier@iro.umontreal.ca> writes: >> The only good arguments I have heard wrt big architectural register >> files has to do with things like Register-Windows and/or optimizing >> CALL/RET interface. > >But even there, it justifies only additional "second-class registers", >i.e. where the set of immediately addressable registers can still be the >same size as usual (e.g. 16 or 32), but you can quickly push some of >those to some kind of "stack" and then pull them back in. Not efficiently. You would have to wait until the last instruction has written back its result, then make the switch, and only then start reading registers from instructions behind the SAVE/RESTORE instruction. Each SAVE and each RESTORE would cost several cycles even on an in-order machine. Not what the mechanism was designed for. >I think you can get similar benefits with "cache-line sized" memory >operations that load/store several registers at a time (assuming you >have good enough store-to-load forwarding). ARM A64's load pair and store pair instructions. >Or even fold those >loads&stores into some kind of CALL/RET instructions, which can let you >start the control-flow part of the CALL before the stores, and similarly >start the loads before the control flow part of the RET is done. In an OoO machine with correct predictions (the usual case), control flow often runs far ahead of functional-unit processing and retirement (and only retirement is architectural execution). Any stores on the predicted control flow will be speculatively performed as soon as their source data is available, and the same goes for loads, with (non)aliases being predicted. Plus really modern machines often can achieve 0-cycle store-to-load forwarding. All of this makes mechanisms like register windows and IA-64's register stack unnecessary. - anton -- 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.' Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>
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| From | scott@slp53.sl.home (Scott Lurndal) |
|---|---|
| Date | 2025-07-17 19:17 +0000 |
| Subject | Re: Register windows (was: The Third Wish) |
| Message-ID | <r%beQ.147382$ivTc.99556@fx43.iad> |
| In reply to | #112613 |
anton@mips.complang.tuwien.ac.at (Anton Ertl) writes: >Stefan Monnier <monnier@iro.umontreal.ca> writes: >>> The only good arguments I have heard wrt big architectural register >>> files has to do with things like Register-Windows and/or optimizing >>> CALL/RET interface. >> >>But even there, it justifies only additional "second-class registers", >>i.e. where the set of immediately addressable registers can still be the >>same size as usual (e.g. 16 or 32), but you can quickly push some of >>those to some kind of "stack" and then pull them back in. > >Not efficiently. You would have to wait until the last instruction >has written back its result, then make the switch, and only then start >reading registers from instructions behind the SAVE/RESTORE >instruction. Each SAVE and each RESTORE would cost several cycles >even on an in-order machine. Not what the mechanism was designed for. > >>I think you can get similar benefits with "cache-line sized" memory >>operations that load/store several registers at a time (assuming you >>have good enough store-to-load forwarding). > >ARM A64's load pair and store pair instructions. ARM A64 has (optional) 64-byte load/store instructions (LD64/ST64), which store/load an entire cache line using 8 GPRs.
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| From | mitchalsup@aol.com (MitchAlsup1) |
|---|---|
| Date | 2025-07-17 19:38 +0000 |
| Subject | Re: Register windows |
| Message-ID | <6a7f2d4cbc31d5089477f3fbb6de2f3a@www.novabbs.org> |
| In reply to | #112613 |
On Thu, 17 Jul 2025 17:38:35 +0000, Anton Ertl wrote: > Stefan Monnier <monnier@iro.umontreal.ca> writes: >>> The only good arguments I have heard wrt big architectural register >>> files has to do with things like Register-Windows and/or optimizing >>> CALL/RET interface. >> >>But even there, it justifies only additional "second-class registers", >>i.e. where the set of immediately addressable registers can still be the >>same size as usual (e.g. 16 or 32), but you can quickly push some of >>those to some kind of "stack" and then pull them back in. > > Not efficiently. You would have to wait until the last instruction > has written back its result, then make the switch, and only then start > reading registers from instructions behind the SAVE/RESTORE > instruction. What you write is INVARIABLY true if SW is the one that has to do this work. The previous value has to leave the register before the new value arrives to be written. It is not true at all if HW is the one doing the work. HW can send out cache line reads for the new data, while the (soon to be) previous values sit in RF--then--as data arrives, HW can readout the previous value while writing in the new values, shipping the previous values to memory as they fill cache line buffers. So, how does HW remember where the registers were in memory--that my friends is called Architecture (not Arch 101, but Arch 315). And that is why My 66000 has HW perform context switching--CPU continues to run while the front end gets the new data ready-- then switches to the new (interrupting) thread in "just a few cycles" including all the Program Status Line stuff which includes Root pointers, priority, privilege, ASID,... Oh, and when done this way--when control arrives at dispatcher/handler it is already re-entrant (no Interrupt/Exception Disable),... > Each SAVE and each RESTORE would cost several cycles > even on an in-order machine. Not what the mechanism was designed for. > >>I think you can get similar benefits with "cache-line sized" memory >>operations that load/store several registers at a time (assuming you >>have good enough store-to-load forwarding). > > ARM A64's load pair and store pair instructions. > >>Or even fold those >>loads&stores into some kind of CALL/RET instructions, which can let you >>start the control-flow part of the CALL before the stores, and similarly >>start the loads before the control flow part of the RET is done. > > In an OoO machine with correct predictions (the usual case), control > flow often runs far ahead of functional-unit processing and retirement Hundreds of instructions--or 15-20 conditional branches. > (and only retirement is architectural execution). Any stores on the > predicted control flow will be speculatively performed as soon as > their source data is available, Where the word "speculation" places a requirement on the CPU to buffer the stored result but no actually update cache/memory until the ST is retired. ST-to-LD forwarding CAN happen. I could argue that this is not what the word "performed" is generally regarded as implying. Instead, I would use the term "conditionally stored" as is what we documented in Mc 88120 (1992) and what the conditional cache did. While sitting in the CC, ST-to-LD forwarding was performed; and after retirement ST.data migrates to the cache/ memory. > and the same goes for loads, with > (non)aliases being predicted. Plus really modern machines often can > achieve 0-cycle store-to-load forwarding. All of this makes > mechanisms like register windows and IA-64's register stack > unnecessary. Along with 0-cycle MOVs, and 0-cycle BC-misprediction recovery. > > - anton
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| From | Stefan Monnier <monnier@iro.umontreal.ca> |
|---|---|
| Date | 2025-07-17 16:18 -0400 |
| Subject | Re: Register windows |
| Message-ID | <jwvh5zainf6.fsf-monnier+comp.arch@gnu.org> |
| In reply to | #112619 |
>> Not efficiently. You would have to wait until the last instruction
>> has written back its result, then make the switch, and only then start
>> reading registers from instructions behind the SAVE/RESTORE
>> instruction.
>
> What you write is INVARIABLY true if SW is the one that has to do
> this work. The previous value has to leave the register before the
> new value arrives to be written.
With register renaming that is not a requirement any more: the new value
is sent to another physical register.
I'm pretty sure you know that, so I wonder what it is that you meant.
Stefan
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