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| From | MitchAlsup <MitchAlsup@aol.com> |
|---|---|
| Newsgroups | comp.arch |
| Subject | Re: New 16 bit CPU by Notch |
| Date | 2012-04-05 09:00 -0700 |
| Organization | http://groups.google.com |
| Message-ID | <16793541.381.1333641651447.JavaMail.geo-discussion-forums@ynib40> (permalink) |
| References | <ggtgp-7600F9.13360904042012@netnews.mchsi.com> |
Can you explain the difference between next-word (0x1F) and litteral (0x20-0x3F) But in general, it looks like you did a nice job. But I think you could get more major op codes if you used a 5-bit a and b fields. This would give you access to all the 'cool' operand types (less the 0x20-0x3F range). Having the PC as a readable and writable operand is BAD NEWS for big OoO. Some constraints, here, might help without eliminating this cool PDP-11-like feature. I suspect that lack of major opcode space is more limiting than lack of 8-bit support (I could be wrong). But you don't have room to load a halfword and then split it into 2 characters--nor room to add it. So, this might come back to haunt you. I further suspect that lack of signed (versus unsigned) will be limiting, certainly by the time you expand to 32-bits it will be. Mitch
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New 16 bit CPU by Notch Brett Davis <ggtgp@yahoo.com> - 2012-04-04 13:36 -0500
Re: New 16 bit CPU by Notch MitchAlsup <MitchAlsup@aol.com> - 2012-04-05 09:00 -0700
Re: New 16 bit CPU by Notch Brett Davis <ggtgp@yahoo.com> - 2012-04-07 02:09 -0500
Re: New 16 bit CPU by Notch EricP <ThatWouldBeTelling@thevillage.com> - 2012-04-05 13:39 -0400
Re: New 16 bit CPU by Notch gavin@allegro.com (Gavin Scott) - 2012-04-25 13:49 -0500
Re: New 16 bit CPU by Notch, version 1.5 Brett Davis <ggtgp@yahoo.com> - 2012-04-27 00:12 -0500
Re: New 16 bit CPU by Notch Walter Banks <walter@bytecraft.com> - 2012-05-28 18:10 -0400
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