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Re: ARM CAS vs LL/SC

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On 5/5/26 21:38, Stephen Fuld wrote:
> On 5/5/2026 7:03 PM, Scott Lurndal wrote:
>> MitchAlsup <user5857@newsgrouper.org.invalid> writes:
>>>
>>> scott@slp53.sl.home (Scott Lurndal) posted:
>>>
>>>> jseigh <jseigh_es00@xemaps.com> writes:
>>>>> Of the possible issues LL/SC might have, did ARM mention the specific
>>>>> reason they add CAS to the architecture?
>>>>
>>>> Scalability.
>>>
>>>
>>>
>>>>                Moving the contention detection to the cache
>>>> is much more bandwidth efficient than swapping cache lines
>>>> between a hundred cores.
>>>
>>> CASs touch the modifiable data fields without write permission,
>>> allowing other cores to touch that data, too. Then, whomever
>>> gets to CAS first {and then gets their CAS addresses to LLC/DRC
>>> first} wins. But you still have the property that only 1 CAS
>>> {in a conflicting group} succeeds.
>>>
>>> I think this second point is dependent on your cache coherent
>>> protocol.
>>>
>>> With this in mind, My 66000 CCP has the ability to request write
>>> permission on a cache line request, but the other end of the
>>> transaction can refuse to send write permission. So, LL requests
>>> write permission, but the 'system' can send the line read-only.
>>> A core can refuse to pass write permission when it has performed
>>> one or more LLs without having run into the SC.
>>>
>>> Given that, one can make LL/SC with that same scaling properties
>>> as CASs.
>>
>> It's still far less convenient to actually use (particularly
>> when CAS is paired with atomic fetch-and-add, bit-set, bit-clear, et alia
>> instructions).
>>
>> And why implement both atomics and LL/SC in a new architecture?
> 
> I think there is an argument for both, though I am not sure how valid it 
>    is.  LL/SC provides a very flexible "framework" for implementing 
> whatever atomic operation seems right for a particular application, but 
> the atomic operations are more efficient if you want to do exactly what 
> they do.
> 
> Think back to the time when the only atomic operation supported was 
> essentially test and set, i.e. before CPUs had atomic fetch and add 
> instructions.  If you wanted the functionality of atomic fetch and add, 
> you would have had to do a TS instruction, followed by a load, then an 
> add, then a store and finally a clear test and set - five instructions. 
> Now think about the same thing if you had LL/SC.  It would be LL, add, 
> SC - three instructions.  Of course, if you had the atomics, it would be 
> one instruction.  Of course, a similar argument applies to a later 
> generation of systems with respect to CAS/DCAS.
> 
> So, having both gives you better efficiency for the cases where your 
> requirements are met by the atomic instructions, but the LL/SC gives you 
> better efficiency when they are not.
> 
> Of course, YMMV, and whether it is worth the hardware and design cost of 
> having both is a separate discussion.
> 
> 

Cavium cnMIPS (OCTEONII/III) implement both.  The LL/SC has lower 
latency for the uncontested path.  The CAS hit the L2.  I'd guess the 
reasoning was the same, CAS wins for higher core counts and guaranteed 
progress?

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ARM CAS vs LL/SC jseigh <jseigh_es00@xemaps.com> - 2026-05-05 17:08 -0400
  Re: ARM CAS vs LL/SC "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-05-05 15:01 -0700
  Re: ARM CAS vs LL/SC scott@slp53.sl.home (Scott Lurndal) - 2026-05-05 22:32 +0000
    Re: ARM CAS vs LL/SC MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-05-06 01:29 +0000
      Re: ARM CAS vs LL/SC scott@slp53.sl.home (Scott Lurndal) - 2026-05-06 02:03 +0000
        Re: ARM CAS vs LL/SC Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2026-05-05 21:38 -0700
          Re: ARM CAS vs LL/SC Kevin Bowling <kevin.bowling@kev009.com> - 2026-05-05 22:54 -0700
            Re: ARM CAS vs LL/SC Terje Mathisen <terje.mathisen@tmsw.no> - 2026-05-06 15:40 +0200
              Re: ARM CAS vs LL/SC MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-05-06 18:31 +0000
                Re: ARM CAS vs LL/SC scott@slp53.sl.home (Scott Lurndal) - 2026-05-06 18:54 +0000
                Re: ARM CAS vs LL/SC MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-05-06 19:48 +0000
              Re: ARM CAS vs LL/SC "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-05-08 22:11 -0700
            Re: ARM CAS vs LL/SC scott@slp53.sl.home (Scott Lurndal) - 2026-05-06 14:19 +0000
              Re: ARM CAS vs LL/SC jseigh <jseigh_es00@xemaps.com> - 2026-05-06 18:30 -0400
                Re: ARM CAS vs LL/SC "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-05-06 21:50 -0700
                Re: ARM CAS vs LL/SC jseigh <jseigh_es00@xemaps.com> - 2026-05-07 17:34 -0400
                Re: ARM CAS vs LL/SC "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-05-08 13:43 -0700
                Re: ARM CAS vs LL/SC MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-05-08 22:18 +0000
                Re: ARM CAS vs LL/SC "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-05-08 22:06 -0700
              Re: ARM CAS vs LL/SC Paul Clayton <paaronclayton@gmail.com> - 2026-05-10 20:19 -0400
                Re: ARM CAS vs LL/SC scott@slp53.sl.home (Scott Lurndal) - 2026-05-11 14:38 +0000
                Re: ARM CAS vs LL/SC Paul Clayton <paaronclayton@gmail.com> - 2026-05-13 19:28 -0400
                Re: ARM CAS vs LL/SC MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-05-14 01:48 +0000
                Re: ARM CAS vs LL/SC Paul Clayton <paaronclayton@gmail.com> - 2026-05-20 19:24 -0400
                Re: ARM CAS vs LL/SC "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-05-14 00:49 -0700
                Re: ARM CAS vs LL/SC "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-05-14 00:58 -0700
                Re: ARM CAS vs LL/SC Paul Clayton <paaronclayton@gmail.com> - 2026-05-20 19:47 -0400
                Re: ARM CAS vs LL/SC Paul Clayton <paaronclayton@gmail.com> - 2026-05-20 19:33 -0400
                Re: ARM CAS vs LL/SC scott@slp53.sl.home (Scott Lurndal) - 2026-05-21 20:17 +0000
                Re: ARM CAS vs LL/SC MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-05-22 17:38 +0000
                Re: ARM CAS vs LL/SC scott@slp53.sl.home (Scott Lurndal) - 2026-05-14 15:03 +0000
                Re: ARM CAS vs LL/SC Paul Clayton <paaronclayton@gmail.com> - 2026-05-20 20:04 -0400
                Re: ARM CAS vs LL/SC scott@slp53.sl.home (Scott Lurndal) - 2026-05-21 20:22 +0000
                Re: ARM CAS vs LL/SC MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-05-22 17:42 +0000

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