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configuring an Efinix T20

From john larkin <jl@650pot.com>
Newsgroups sci.electronics.design, comp.arch.fpga, comp.sys.raspberry.pi
Subject configuring an Efinix T20
Date 2024-09-06 15:50 -0700
Message-ID <5h0ndj9c0cpc70eh6stoa5qi8371blq7nb@4ax.com> (permalink)

Cross-posted to 3 groups.

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I'm planning to use a Raspberry Pi RP2040 processor chip to configure
and then talk to an Efinix T20-FG256 FPGA.

Has anyone done this, or at least configured a T20 from a
microprocessor? 

The RP2040 only has 30 GPIO pins, and many are dedicated to other
stuff, so we want to share a lot of things on one giant SPI bus,
including the FPGA config and then an SPI port on the FPGA to read and
write registers.

It looks like four of the T20 config pins need pullups. I wonder why
their guidelines show four separate resistors. Why not one resistor?
Why have resistors at all?

SS_N needs a pulldown. Why not ground it?

https://www.dropbox.com/scl/fi/x0gvvwqg42vhryu6610ve/Efinix_Config_1.jpg?rlkey=udy24brtumvdzfd2sp4l6yhwf&raw=1


It's always a moment to celebrate when a "config done" LED lights up.

I could easily get this wrong, so it would be great if I posted some
schematics and notes and someone could eyeball them for me.

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Thread

configuring an Efinix T20 john larkin <jl@650pot.com> - 2024-09-06 15:50 -0700
  Re: configuring an Efinix T20 John R Walliker <jrwalliker@gmail.com> - 2024-09-07 15:19 +0100
    Re: configuring an Efinix T20 john larkin <jlarkin_highland_tech> - 2024-09-07 08:58 -0700
      Re: configuring an Efinix T20 John R Walliker <jrwalliker@gmail.com> - 2024-09-07 19:29 +0100
        Re: configuring an Efinix T20 john larkin <jl@650pot.com> - 2024-09-09 12:20 -0700
          Re: configuring an Efinix T20 piglet <erichpwagner@hotmail.com> - 2024-09-09 20:02 +0000
            Re: configuring an Efinix T20 john larkin <jl@650pot.com> - 2024-09-09 14:17 -0700
  Re: configuring an Efinix T20 Lasse Langwadt <llc@fonz.dk> - 2024-09-12 00:44 +0200

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