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| From | Bonita Montero <Bonita.Montero@gmail.com> |
| Newsgroups | comp.arch.arithmetic |
| Subject | Re: Quiet NaN question |
| Date | Sat, 18 Jun 2016 12:22:47 +0200 |
| Organization | albasani.net |
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Am 18.06.2016 um 12:15 schrieb Bonita Montero: > My SSE-FPU generates the following NaNs: > > * When I do a any basic dual operation like ADDSD, SUBSD, MULSD or DIVSD > and one of both operands is a NaN, the result has the sign of the NaN > -operand and the lower 51 bits of the mantissa of the result is loa- > ded with the lower 51 bits of the mantissa of the NaN-operand. And: * If any operand is a signalling NaN, the result becomes a quiet NaN if the exception isn't masked. -- http://facebook.com/bonita.montero/
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Quiet NaN question Bonita Montero <Bonita.Montero@gmail.com> - 2016-06-18 12:15 +0200
Re: Quiet NaN question Bonita Montero <Bonita.Montero@gmail.com> - 2016-06-18 12:22 +0200
Re: Quiet NaN question Terje Mathisen <terje.mathisen@tmsw.no> - 2016-06-19 01:08 +0300
Re: Quiet NaN question Bonita Montero <Bonita.Montero@gmail.com> - 2016-06-19 13:32 +0200
Re: Quiet NaN question Terje Mathisen <terje.mathisen@tmsw.no> - 2016-06-20 01:10 +0200
Re: Quiet NaN question bde@etaplex.bde.org (Bruce Evans) - 2016-06-20 04:24 +0000
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