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Quiet NaN question

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   My SSE-FPU generates the following NaNs:

* When I do a any basic dual operation like ADDSD, SUBSD, MULSD or DIVSD
   and one of both operands is a NaN, the result has the sign of the NaN
   -operand and the lower 51 bits of the mantissa of the result is loa-
   ded with the lower 51 bits of the mantissa of the NaN-operand.
* When both operations are NaN, the result is loaded with the sign of
   the destination-register and the lower 51 bits of the result-mantissa
   is loaded with the lower 51 bits of the destination-register before
   the operation. So the associative law doesn't count here and the order
   of the operands in a multiplication does count!
* When I do a SQRTSD on a NaN-value, the result has the sign of the
   NaN-operand and the lower 51 bits of the result is loaded with the
   lower 51 bits of the operand.
* When I do a multiplication of infinity with zero or infinity, I always
   get -NaN as a result (binary representation 0xFFF8000000000000u).

Is this behaviour determined anywhere in the IEEE-754-standard?

-- 
http://facebook.com/bonita.montero/

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Quiet NaN question Bonita Montero <Bonita.Montero@gmail.com> - 2016-06-18 12:15 +0200
  Re: Quiet NaN question Bonita Montero <Bonita.Montero@gmail.com> - 2016-06-18 12:22 +0200
  Re: Quiet NaN question Terje Mathisen <terje.mathisen@tmsw.no> - 2016-06-19 01:08 +0300
    Re: Quiet NaN question Bonita Montero <Bonita.Montero@gmail.com> - 2016-06-19 13:32 +0200
      Re: Quiet NaN question Terje Mathisen <terje.mathisen@tmsw.no> - 2016-06-20 01:10 +0200
        Re: Quiet NaN question bde@etaplex.bde.org (Bruce Evans) - 2016-06-20 04:24 +0000

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