Path: csiph.com!1.us.feeder.erje.net!feeder.erje.net!2.us.feeder.erje.net!news.glorb.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!spln!extra.newsguy.com!newsp.newsguy.com!drn From: Winfield Hill Newsgroups: sci.electronics.design Subject: Re: bad, better delay circuits Date: 20 Mar 2017 12:22:18 -0700 Organization: Rowland Institute Lines: 25 Message-ID: References: <1roqcclua35sdrn6jduc9q0folr3fg8oqu@4ax.com> <58cf33fb$0$62260$b1db1813$65575428@news.astraweb.com> NNTP-Posting-Host: p34077a65cd45e41d20f0fddd6ce12f8532abf837aae78b62.newsdawg.com User-Agent: Direct Read News 5.60 X-Received-Bytes: 1291 X-Received-Body-CRC: 4013387611 Xref: csiph.com sci.electronics.design:452764 Clifford Heath wrote... > >On 20/03/17 11:54, Winfield Hill wrote: >> John Larkin wrote... >>> >>> The problem is the mosfet. Its turn-off >>> behavior is ugly in a very complex way. >>> Diodes are easier to understand. >> >> The nice thing about tri-state gates, they have >> awesome optimized low-voltage 3.3V mosfets to >> pull down the cap, and optimized gate drive >> to turn them off. Can't match w/ a discrete. > > You don't lose anything by having a high-side > MOSFET connected (though off)? The issue would only be the gate output node's off capacitance. I found it to be quite small, although I haven't measured it, should do so. -- Thanks, - Win