Path: csiph.com!weretis.net!feeder6.news.weretis.net!news.glorb.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!spln!extra.newsguy.com!newsp.newsguy.com!drn From: Winfield Hill Newsgroups: sci.electronics.design Subject: Re: ping Win, SiC fets Date: 3 Nov 2016 11:29:22 -0700 Organization: Rowland Institute Lines: 22 Message-ID: References: <7ium1cd84a5cluoauv6kpl1u26tin277bm@4ax.com> NNTP-Posting-Host: p6c0d4088b18c120a7f531fe291f2d9f9b4d1c5d23936237e.newsdawg.com User-Agent: Direct Read News 5.60 X-Received-Bytes: 1592 X-Received-Body-CRC: 1655316321 Xref: csiph.com sci.electronics.design:433698 John Larkin wrote... > > Can you reveal what you're using for gate drivers? Hah, I now have 6 different versions of the board, with six different gate-driver approaches, trying to reach my 10MHz repetition-rate goal. I'm not happy with any of them. My latest scheme gives up on TO-220 driver ICs, and uses a fast recent-vintage driver. I suffer its poor thermal properties, and add NPN and PNP emitter-followers to handle some of the C V^2 f power dissipation. Note that SiC MOSFETs have 1/4 the capacitance but require twice the gate voltage, hence 4x more power killing that advantage. The dissipation is now shared by two 1812 resistors, two sot-223 BJTs and the driver IC. The latter has a heatsink. -- Thanks, - Win