Path: csiph.com!feeder.erje.net!2.eu.feeder.erje.net!news2.arglkargh.de!news.mixmin.net!aioe.org!bofh.it!news.nic.it!robomod From: Mathieu Poirier Newsgroups: linux.kernel Subject: Re: [PATCH V2 1/3] arm64: dts: Add basic DT to support Spreadtrum's SP9860G Date: Tue, 21 Feb 2017 17:30:02 +0100 Message-ID: References: Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=pvybN+yr9KE1ZuCtfv9N+adhwdSvqYT+jUXDj+xxa7Q=; b=RXwRxelTzbmE8LoJHS8xOIjSLRvtyTwuKaQqaPyOy5VZPHGjhgGWaJzv5Bc4uqEUs5 I6XMFncKjjxXbNdyD6KnjuQqx48ZEuox8T/7czfmbtt/nIV5XP+vXWNGqnWw1BBl+dNf HZga6zKJckX+iFcOtviDTYwWlLCbkQaHeWkOo= X-Google-Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=pvybN+yr9KE1ZuCtfv9N+adhwdSvqYT+jUXDj+xxa7Q=; b=fCZyXGiXmN3NEdPCfSEph2sa5TFOrRR8vLhdB1rv6uGoYuVnwtrBqarlyJvU38p0g+ QaOuDBCHyGbMc5JgH7Wb51Au5Ku8UV5n/EU2f1FkI7pfIFXk1ZdYadd/e6/i9WVCpSrV psqnFvbKZ5jNAH2S4GJaC1fZaPCHxj82g7AqCVMNFDPi2k8Iwdq8M4T0UNEd17rcZ7f9 xn/70F6mWjLfljA890zvUNzdMYv7bb1oK1wJkOCRUS1An2kdmbtzByQdhSkz83zppFjs y0D8xgO71RpIg4YFbJ7DzjegrjNNO75I4l9I+3FTjdGCSwnban8Z/VHz8AmJwp07vWsu RJYw== X-Gm-Message-State: AMke39n0vj+OOY/wNj0aUe/RG/+NuYGfFA/FHIYcRV6BbqKE+2xD2Yd88yRz9XO66/z3+8+s X-Received: by 10.36.134.1 with SMTP id u1mr15450659itd.104.1487694468299; Tue, 21 Feb 2017 08:27:48 -0800 (PST) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.24 (2015-08-30) Sender: robomod@news.nic.it List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Approved: robomod@news.nic.it Lines: 735 Organization: linux.* mail to news gateway X-Original-Cc: robh+dt@kernel.org, mark.rutland@arm.com, gregkh@linuxfoundation.org, catalin.marinas@arm.com, will.deacon@arm.com, arnd@arndb.de, devicetree@vger.kernel.org, orson.zhai@spreadtrum.com, zhang.lyra@gmail.com, linux-kernel@vger.kernel.org, sudeep.holla@arm.com, linux-arm-kernel@lists.infradead.org X-Original-Date: Tue, 21 Feb 2017 09:27:44 -0700 X-Original-Message-ID: <20170221162744.GA29581@linaro.org> X-Original-References: <1487660104-15693-1-git-send-email-chunyan.zhang@spreadtrum.com> <1487660104-15693-2-git-send-email-chunyan.zhang@spreadtrum.com> X-Original-Sender: linux-kernel-owner@vger.kernel.org Xref: csiph.com linux.kernel:1585496 On Tue, Feb 21, 2017 at 02:55:02PM +0800, Chunyan Zhang wrote: > From: Orson Zhai Hello Chunyan, > > SC9860G is a 8 cores of A53 SoC with 4G LTE support SoC from Spreadtrum. > > According to regular hierarchy of sprd dts, whale2.dtsi contains SoC > peripherals IP nodes, sc9860.dtsi contains stuff related to ARM core stuff > and sp9860g dts is for the board level. > > Signed-off-by: Orson Zhai > Signed-off-by: Chunyan Zhang > --- > arch/arm64/boot/dts/sprd/Makefile | 3 +- > arch/arm64/boot/dts/sprd/sc9860.dtsi | 531 ++++++++++++++++++++++++++++++ > arch/arm64/boot/dts/sprd/sp9860g-1h10.dts | 56 ++++ > arch/arm64/boot/dts/sprd/whale2.dtsi | 70 ++++ > 4 files changed, 659 insertions(+), 1 deletion(-) > create mode 100644 arch/arm64/boot/dts/sprd/sc9860.dtsi > create mode 100644 arch/arm64/boot/dts/sprd/sp9860g-1h10.dts > create mode 100644 arch/arm64/boot/dts/sprd/whale2.dtsi > > diff --git a/arch/arm64/boot/dts/sprd/Makefile b/arch/arm64/boot/dts/sprd/Makefile > index b658c5e..f0535e6 100644 > --- a/arch/arm64/boot/dts/sprd/Makefile > +++ b/arch/arm64/boot/dts/sprd/Makefile > @@ -1,4 +1,5 @@ > -dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb > +dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb \ > + sp9860g-1h10.dtb > > always := $(dtb-y) > subdir-y := $(dts-dirs) > diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi > new file mode 100644 > index 0000000..73deb4e > --- /dev/null > +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi > @@ -0,0 +1,531 @@ > +/* > + * Spreadtrum SP9860 SoC DTS file > + * > + * Copyright (C) 2016, Spreadtrum Communications Inc. > + * > + * This file is licensed under a dual GPLv2 or X11 license. > + */ > + > +#include > +#include "whale2.dtsi" > + > +/ { > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&CPU0>; > + }; > + core1 { > + cpu = <&CPU1>; > + }; > + core2 { > + cpu = <&CPU2>; > + }; > + core3 { > + cpu = <&CPU3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&CPU4>; > + }; > + core1 { > + cpu = <&CPU5>; > + }; > + core2 { > + cpu = <&CPU6>; > + }; > + core3 { > + cpu = <&CPU7>; > + }; > + }; > + }; > + > + CPU0: cpu@530000 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x530000>; > + enable-method = "psci"; > + cpu-idle-states = <&CORE_PD &CLUSTER_PD>; > + }; > + > + CPU1: cpu@530001 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x530001>; > + enable-method = "psci"; > + cpu-idle-states = <&CORE_PD &CLUSTER_PD>; > + }; > + > + CPU2: cpu@530002 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x530002>; > + enable-method = "psci"; > + cpu-idle-states = <&CORE_PD &CLUSTER_PD>; > + }; > + > + CPU3: cpu@530003 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x530003>; > + enable-method = "psci"; > + cpu-idle-states = <&CORE_PD &CLUSTER_PD>; > + }; > + > + CPU4: cpu@530100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x530100>; > + enable-method = "psci"; > + cpu-idle-states = <&CORE_PD &CLUSTER_PD>; > + }; > + > + CPU5: cpu@530101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x530101>; > + enable-method = "psci"; > + cpu-idle-states = <&CORE_PD &CLUSTER_PD>; > + }; > + > + CPU6: cpu@530102 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x530102>; > + enable-method = "psci"; > + cpu-idle-states = <&CORE_PD &CLUSTER_PD>; > + }; > + > + CPU7: cpu@530103 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x530103>; > + enable-method = "psci"; > + cpu-idle-states = <&CORE_PD &CLUSTER_PD>; > + }; > + }; > + > + idle-states{ > + entry-method = "arm,psci"; > + > + CORE_PD: core_pd { > + compatible = "arm,idle-state"; > + entry-latency-us = <1000>; > + exit-latency-us = <700>; > + min-residency-us = <2500>; > + local-timer-stop; > + arm,psci-suspend-param = <0x00010002>; > + }; > + > + CLUSTER_PD: cluster_pd { > + compatible = "arm,idle-state"; > + entry-latency-us = <1000>; > + exit-latency-us = <1000>; > + min-residency-us = <3000>; > + local-timer-stop; > + arm,psci-suspend-param = <0x01010003>; > + }; > + }; > + > + gic: interrupt-controller@12001000 { > + compatible = "arm,gic-400"; > + reg = <0 0x12001000 0 0x1000>, > + <0 0x12002000 0 0x2000>, > + <0 0x12004000 0 0x2000>, > + <0 0x12006000 0 0x2000>; > + #interrupt-cells = <3>; > + interrupt-controller; > + interrupts = + | IRQ_TYPE_LEVEL_HIGH)>; > + }; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = + | IRQ_TYPE_LEVEL_LOW)>, > + + | IRQ_TYPE_LEVEL_LOW)>, > + + | IRQ_TYPE_LEVEL_LOW)>, > + + | IRQ_TYPE_LEVEL_LOW)>; > + }; > + > + pmu { > + compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; > + interrupts = , > + , > + , > + , > + , > + , > + , > + ; > + interrupt-affinity = <&CPU0>, > + <&CPU1>, > + <&CPU2>, > + <&CPU3>, > + <&CPU4>, > + <&CPU5>, > + <&CPU6>, > + <&CPU7>; > + }; > + > + soc { > + soc_funnel: funnel@10001000 { There is no need for a label ("soc_funnel) before the device name if that device is not referenced elsewhere in the DTS. The same comment applies to most of the component listed below. > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0 0x10001000 0 0x1000>; > + clocks = <&ext_26m>; > + clock-names = "apb_pclk"; > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + soc_funnel_out_port: endpoint { > + remote-endpoint = <&etb_in>; > + }; > + }; > + > + port@1 { > + reg = <0>; > + soc_funnel_in_port: endpoint { > + slave-mode; > + remote-endpoint = > + <&main_funnel_out_port>; > + }; > + }; > + }; > + }; > + > + etb@10003000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0 0x10003000 0 0x1000>; > + clocks = <&ext_26m>; > + clock-names = "apb_pclk"; > + port { > + etb_in: endpoint { > + slave-mode; > + remote-endpoint = > + <&soc_funnel_out_port>; > + }; > + }; > + }; > + > + cluster0_funnel: funnel@11001000 { > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0 0x11001000 0 0x1000>; > + clocks = <&ext_26m>; > + clock-names = "apb_pclk"; > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + cluster0_funnel_out_port: endpoint { > + remote-endpoint = > + <&cluster0_etf_in>; > + }; > + }; > + > + port@1 { > + reg = <0>; > + cluster0_funnel_in_port0: endpoint { > + slave-mode; > + remote-endpoint = <&etm0_out>; > + }; > + }; > + > + port@2 { > + reg = <1>; > + cluster0_funnel_in_port1: endpoint { > + slave-mode; > + remote-endpoint = <&etm1_out>; > + }; > + }; > + > + port@3 { > + reg = <2>; > + cluster0_funnel_in_port2: endpoint { > + slave-mode; > + remote-endpoint = <&etm2_out>; > + }; > + }; > + > + port@4 { > + reg = <4>; > + cluster0_funnel_in_port3: endpoint { > + slave-mode; > + remote-endpoint = <&etm3_out>; > + }; > + }; > + }; > + }; > + > + cluster1_funnel: funnel@11002000 { > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0 0x11002000 0 0x1000>; > + clocks = <&ext_26m>; > + clock-names = "apb_pclk"; > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + cluster1_funnel_out_port: endpoint { > + remote-endpoint = > + <&cluster1_etf_in>; > + }; > + }; > + > + port@1 { > + reg = <0>; > + cluster1_funnel_in_port0: endpoint { > + slave-mode; > + remote-endpoint = <&etm4_out>; > + }; > + }; > + > + port@2 { > + reg = <1>; > + cluster1_funnel_in_port1: endpoint { > + slave-mode; > + remote-endpoint = <&etm5_out>; > + }; > + }; > + > + port@3 { > + reg = <2>; > + cluster1_funnel_in_port2: endpoint { > + slave-mode; > + remote-endpoint = <&etm6_out>; > + }; > + }; > + > + port@4 { > + reg = <3>; > + cluster1_funnel_in_port3: endpoint { > + slave-mode; > + remote-endpoint = <&etm7_out>; > + }; > + }; > + }; > + }; > + > + cluster0_etf: etf@11003000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0 0x11003000 0 0x1000>; > + clocks = <&ext_26m>; > + clock-names = "apb_pclk"; > + > + port@0 { > + cluster0_etf_out: endpoint { > + remote-endpoint = > + <&main_funnel_in_port0>; > + }; > + }; > + > + port@1 { > + cluster0_etf_in: endpoint { > + slave-mode; > + remote-endpoint = > + <&cluster0_funnel_out_port>; > + }; > + }; > + }; > + > + cluster1_etf: etf@11004000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0 0x11004000 0 0x1000>; > + clocks = <&ext_26m>; > + clock-names = "apb_pclk"; > + > + port@0 { > + cluster1_etf_out: endpoint { > + remote-endpoint = > + <&main_funnel_in_port1>; > + }; > + }; > + > + port@1 { > + cluster1_etf_in: endpoint { > + slave-mode; > + remote-endpoint = > + <&cluster1_funnel_out_port>; > + }; > + }; > + }; When more than one port is present it is customary to add another level of imbrication like it is done for funnels above: "ports {" port@0 { ... port@1 { ... } The same comment applies to both etf. > + > + main_funnel: funnel@11005000 { > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0 0x11005000 0 0x1000>; > + clocks = <&ext_26m>; > + clock-names = "apb_pclk"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + main_funnel_out_port: endpoint { > + remote-endpoint = > + <&soc_funnel_in_port>; > + }; > + }; > + > + port@1 { > + reg = <0>; > + main_funnel_in_port0: endpoint { > + slave-mode; > + remote-endpoint = > + <&cluster0_etf_out>; > + }; > + }; > + > + port@2 { > + reg = <1>; > + main_funnel_in_port1: endpoint { > + slave-mode; > + remote-endpoint = > + <&cluster1_etf_out>; > + }; > + }; > + }; > + }; > + > + etm@11440000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x11440000 0 0x1000>; > + cpu = <&CPU0>; > + clocks = <&ext_26m>; > + clock-names = "apb_pclk"; > + > + port { > + etm0_out: endpoint { > + remote-endpoint = > + <&cluster0_funnel_in_port0>; > + }; > + }; > + }; > + > + etm@11540000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x11540000 0 0x1000>; > + cpu = <&CPU1>; > + clocks = <&ext_26m>; > + clock-names = "apb_pclk"; > + > + port { > + etm1_out: endpoint { > + remote-endpoint = > + <&cluster0_funnel_in_port1>; > + }; > + }; > + }; > + > + etm@11640000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x11640000 0 0x1000>; > + cpu = <&CPU2>; > + clocks = <&ext_26m>; > + clock-names = "apb_pclk"; > + > + port { > + etm2_out: endpoint { > + remote-endpoint = > + <&cluster0_funnel_in_port2>; > + }; > + }; > + }; > + > + etm@11740000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x11740000 0 0x1000>; > + cpu = <&CPU3>; > + clocks = <&ext_26m>; > + clock-names = "apb_pclk"; > + > + port { > + etm3_out: endpoint { > + remote-endpoint = > + <&cluster0_funnel_in_port3>; > + }; > + }; > + }; > + > + etm@11840000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x11840000 0 0x1000>; > + cpu = <&CPU4>; > + clocks = <&ext_26m>; > + clock-names = "apb_pclk"; > + > + port { > + etm4_out: endpoint { > + remote-endpoint = > + <&cluster1_funnel_in_port0>; > + }; > + }; > + }; > + > + etm@11940000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x11940000 0 0x1000>; > + cpu = <&CPU5>; > + clocks = <&ext_26m>; > + clock-names = "apb_pclk"; > + > + port { > + etm5_out: endpoint { > + remote-endpoint = > + <&cluster1_funnel_in_port1>; > + }; > + }; > + }; > + > + etm@11a40000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x11a40000 0 0x1000>; > + cpu = <&CPU6>; > + clocks = <&ext_26m>; > + clock-names = "apb_pclk"; > + > + port { > + etm6_out: endpoint { > + remote-endpoint = > + <&cluster1_funnel_in_port2>; > + }; > + }; > + }; > + > + etm@11b40000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x11b40000 0 0x1000>; > + cpu = <&CPU7>; > + clocks = <&ext_26m>; > + clock-names = "apb_pclk"; > + > + port { > + etm7_out: endpoint { > + remote-endpoint = > + <&cluster1_funnel_in_port3>; > + }; > + }; > + }; > + }; > +}; > diff --git a/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts > new file mode 100644 > index 0000000..5faa452 > --- /dev/null > +++ b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts > @@ -0,0 +1,56 @@ > +/* > + * Spreadtrum SP9860g board DTS file > + * > + * Copyright (C) 2017, Spreadtrum Communications Inc. > + * > + * This file is licensed under a dual GPLv2 or X11 license. > + */ > + > +/dts-v1/; > + > +#include "sc9860.dtsi" > + > +/ { > + model = "Spreadtrum SP9860G 3GFHD Board"; > + > + compatible = "sprd,sp9860g-1h10", "sprd,sc9860"; > + > + aliases { > + serial0 = &uart0; /* for Bluetooth */ > + serial1 = &uart1; /* UART console */ > + serial2 = &uart2; /* Reserved */ > + serial3 = &uart3; /* for GPS */ > + }; > + > + memory{ > + device_type = "memory"; > + reg = <0x0 0x80000000 0 0x60000000>, > + <0x1 0x80000000 0 0x60000000>; > + }; > + > + chosen { > + stdout-path = "serial1:115200n8"; > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > + > +&uart1 { > + status = "okay"; > +}; > + > +&uart2 { > + status = "okay"; > +}; > + > +&uart3 { > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi > new file mode 100644 > index 0000000..64f06d9 > --- /dev/null > +++ b/arch/arm64/boot/dts/sprd/whale2.dtsi > @@ -0,0 +1,70 @@ > +/* > + * Spreadtrum Whale2 SoC platform peripherals DTS file > + * > + * Copyright (C) 2016, Spreadtrum Communications Inc. > + * > + * This file is licensed under a dual GPLv2 or X11 license. > + */ > + > +/ { > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + soc: soc { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + ap-apb { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x0 0x70000000 0x10000000>; > + > + uart0: serial@70000000 { > + compatible = "sprd,sc9838-uart", > + "sprd,sc9836-uart"; > + reg = <0x000000 0x100>; > + interrupts = ; > + clocks = <&ext_26m>; > + status = "disabled"; > + }; > + > + uart1: serial@70100000 { > + compatible = "sprd,sc9838-uart", > + "sprd,sc9836-uart"; > + reg = <0x100000 0x100>; > + interrupts = ; > + clocks = <&ext_26m>; > + status = "disabled"; > + }; > + > + uart2: serial@70200000 { > + compatible = "sprd,sc9838-uart", > + "sprd,sc9836-uart"; > + reg = <0x200000 0x100>; > + interrupts = ; > + clocks = <&ext_26m>; > + status = "disabled"; > + }; > + > + uart3: serial@70300000 { > + compatible = "sprd,sc9838-uart", > + "sprd,sc9836-uart"; > + reg = <0x300000 0x100>; > + interrupts = ; > + clocks = <&ext_26m>; > + status = "disabled"; > + }; > + }; > + > + ext_26m: ext-26m { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <26000000>; > + clock-output-names = "ext_26m"; > + }; > + }; > +}; > -- > 2.7.4 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel