Path: csiph.com!eternal-september.org!feeder.eternal-september.org!aioe.org!gothmog.csi.it!bofh.it!news.nic.it!robomod From: Greg Kroah-Hartman Newsgroups: linux.kernel Subject: [PATCH 4.4 051/118] ARM: imx6: add missing BM_CLPCR_BYPASS_PMIC_READY setting for imx6sx Date: Thu, 22 Sep 2016 19:40:01 +0200 Message-ID: References: X-Mailer: git-send-email 2.10.0 User-Agent: quilt/0.64 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Sender: robomod@news.nic.it List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Approved: robomod@news.nic.it Lines: 36 Organization: linux.* mail to news gateway X-Original-Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Anson Huang , Peter Chen , Shawn Guo X-Original-Date: Thu, 22 Sep 2016 19:29:11 +0200 X-Original-Message-ID: <20160922172941.357401452@linuxfoundation.org> X-Original-References: <20160922172938.643879685@linuxfoundation.org> X-Original-Sender: linux-kernel-owner@vger.kernel.org Xref: csiph.com linux.kernel:1489120 4.4-stable review patch. If anyone has any objections, please let me know. ------------------ From: Anson Huang commit 8aade778f787305fdbfd3c1d54e6b583601b5902 upstream. i.MX6SX has bypass PMIC ready function, as this function is normally NOT enabled on the board design, so we need to bypass the PMIC ready pin check during DSM mode resume flow, otherwise, the internal DSM resume logic will be waiting for this signal to be ready forever and cause resume fail. Signed-off-by: Anson Huang Fixes: ff843d621bfc ("ARM: imx: add suspend support for i.mx6sx") Tested-by: Peter Chen Signed-off-by: Shawn Guo Signed-off-by: Greg Kroah-Hartman --- arch/arm/mach-imx/pm-imx6.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/arch/arm/mach-imx/pm-imx6.c +++ b/arch/arm/mach-imx/pm-imx6.c @@ -310,7 +310,7 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode m val |= 0x3 << BP_CLPCR_STBY_COUNT; val |= BM_CLPCR_VSTBY; val |= BM_CLPCR_SBYOS; - if (cpu_is_imx6sl()) + if (cpu_is_imx6sl() || cpu_is_imx6sx()) val |= BM_CLPCR_BYPASS_PMIC_READY; if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul()) val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;