Path: csiph.com!feeder.erje.net!1.us.feeder.erje.net!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!news.mixmin.net!aioe.org!gothmog.csi.it!bofh.it!news.nic.it!robomod From: Kedareswara rao Appana Newsgroups: linux.kernel Subject: [PATCH] dmaengine: xilinx: Fix race condition in axi dma cyclic dma mode Date: Sat, 09 Jul 2016 10:50:01 +0200 Message-ID: X-Original-To: , , , , , , , Authentication-Results: spf=pass (sender IP is 149.199.60.100) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-Spf: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.100 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.100; helo=xsj-pvapsmtpgw02; X-Mailer: git-send-email 2.1.1 X-Rcis-Action: ALLOW X-Tm-As-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22438.005 X-Tm-As-User-Approved-Sender: Yes;Yes X-Ms-Office365-Filtering-Ht: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.100;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(7916002)(2980300002)(438002)(189002)(199003)(4326007)(305945005)(19580395003)(11100500001)(81156014)(48376002)(52956003)(19580405001)(36386004)(7846002)(5003940100001)(50466002)(42186005)(87936001)(81166006)(36756003)(8676002)(229853001)(356003)(33646002)(86362001)(2201001)(2906002)(45336002)(103686003)(63266004)(46386002)(189998001)(50986999)(90966002)(106466001)(92566002)(8936002)(586003)(5001770100001)(50226002)(47776003)(107986001)(5001870100001)(2101003);DIR:OUT;SFP:1101;SCL:1;SRVR:SN1NAM02HT149;H:xsj-pvapsmtpgw02;FPR:;SPF:Pass;PTR:xapps1.xilinx.com,unknown-60-100.xilinx.com;MX:1;A:1;CAT:NONE;LANG:en;CAT:NONE; MIME-Version: 1.0 Content-Type: text/plain X-Ms-Office365-Filtering-Correlation-ID: 030f3936-3439-4842-ca31-08d3a7d49c2e X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:SN1NAM02HT149; X-Microsoft-Antispam-Prvs: X-Exchange-Antispam-Report-Test: UriScan:(192813158149592); X-Exchange-Antispam-Report-Cfa-Test: BCL:0;PCL:0;RULEID:(601004)(2401047)(13024025)(13017025)(13015025)(13023025)(8121501046)(5005006)(13018025)(10201501046)(3002001)(6055026);SRVR:SN1NAM02HT149;BCL:0;PCL:0;RULEID:;SRVR:SN1NAM02HT149; X-Forefront-Prvs: 0998671D02 X-Originatororg: xilinx.com X-Ms-Exchange-Crosstenant-Originalarrivaltime: 09 Jul 2016 08:39:58.1151 (UTC) X-Ms-Exchange-Crosstenant-ID: 657af505-d5df-48d0-8300-c31994686c5c X-Ms-Exchange-Crosstenant-Originalattributedtenantconnectingip: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.100];Helo=[xsj-pvapsmtpgw02] X-Ms-Exchange-Crosstenant-Fromentityheader: HybridOnPrem X-Ms-Exchange-Transport-Crosstenantheadersstamped: SN1NAM02HT149 Sender: robomod@news.nic.it List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Approved: robomod@news.nic.it Lines: 39 Organization: linux.* mail to news gateway X-Original-Cc: , , X-Original-Date: Sat, 9 Jul 2016 14:09:48 +0530 X-Original-Message-ID: <1468053588-18357-1-git-send-email-appanad@xilinx.com> X-Original-Sender: linux-kernel-owner@vger.kernel.org Xref: csiph.com linux.kernel:1439920 In cyclic DMA mode need to link the tail bd segment with the head bd segment to process bd's in cyclic. Current driver is doing this only for tx channel needs to update the same for rx channel case also. This patch fixes the same. Signed-off-by: Kedareswara rao Appana --- drivers/dma/xilinx/xilinx_dma.c | 9 +++++---- 1 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index cf47347..4e223d0 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1895,14 +1895,15 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic( reg |= XILINX_DMA_CR_CYCLIC_BD_EN_MASK; dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); + segment = list_last_entry(&desc->segments, + struct xilinx_axidma_tx_segment, + node); + segment->hw.next_desc = (u32) head_segment->phys; + /* For the last DMA_MEM_TO_DEV transfer, set EOP */ if (direction == DMA_MEM_TO_DEV) { head_segment->hw.control |= XILINX_DMA_BD_SOP; - segment = list_last_entry(&desc->segments, - struct xilinx_axidma_tx_segment, - node); segment->hw.control |= XILINX_DMA_BD_EOP; - segment->hw.next_desc = (u32) head_segment->phys; } return &desc->async_tx; -- 1.7.1