Path: csiph.com!news.mixmin.net!news2.arglkargh.de!news.karotte.org!fu-berlin.de!bofh.it!news.nic.it!robomod From: Simon Richter Newsgroups: linux.debian.bugs.dist,linux.debian.kernel Subject: Bug#1015871: Enabling PCI_P2PDMA for distro kernels? Date: Thu, 26 Oct 2023 01:50:01 +0200 Message-ID: References: X-Original-To: Lukas Wunner , Logan Gunthorpe X-Mailbox-Line: From debian-bugs-dist-request@lists.debian.org Wed Oct 25 23:45:09 2023 Old-Return-Path: X-Spam-Flag: NO X-Spam-Score: -4.2 Reply-To: Simon Richter , 1015871@bugs.debian.org Resent-To: debian-bugs-dist@lists.debian.org Resent-Cc: Debian Kernel Team X-Debian-Pr-Message: followup 1015871 X-Debian-Pr-Package: src:linux X-Debian-Pr-Source: linux MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Debian-Message: from BTS X-Mailing-List: archive/latest/1803150 List-ID: List-URL: Approved: robomod@news.nic.it Lines: 36 Organization: linux.* mail to news gateway Sender: robomod@news.nic.it X-Original-Cc: Uwe =?UTF-8?Q?Kleine-K=C3=B6nig?= , Bjorn Helgaas , Simon Richter , 1015871@bugs.debian.org, linux-pci@vger.kernel.org, Alex Deucher , Krzysztof Wilczy??ski , Emanuele Rocca X-Original-Date: Thu, 26 Oct 2023 08:40:04 +0900 X-Original-Message-ID: <7bf7628c-9d92-4c87-86db-b60c272f59be@debian.org> X-Original-References: <20231025061927.smn5xnwpkasctpn7@pengutronix.de> <20231025171126.GA9661@wunner.de> <165852041410.25326.17973698626515845951.reportbug@lime.hogyros.de> <20231025171126.GA9661@wunner.de> Xref: csiph.com linux.debian.bugs.dist:1172817 linux.debian.kernel:80742 Hi, On 10/26/23 02:11, Lukas Wunner wrote: > This has recently been brought up internally at Intel and nobody could > understand why there's a whitelist in the first place. A long-time PCI > architect told me that Intel silicon validation has been testing P2PDMA > at least since the Lindenhurst days, i.e. since 2005. My PCIe test box generates URE completions in the root complex when I try to address iGPU BARs from an FPGA, and texture fetches from the iGPU that use BAR addresses on the FPGA do not get forwarded (so I venture that is an URE as well). CPU: i3-3225 CPU @ 3.30GHz (fam: 06, model: 3a, stepping: 09) pci 0000:00:00.0: [8086:0150] type 00 class 0x060000 pci 0000:00:01.0: [8086:0151] type 01 class 0x060400 pci 0000:00:02.0: [8086:0162] type 00 class 0x030000 pci 0000:00:14.0: [8086:1e31] type 00 class 0x0c0330 pci 0000:00:16.0: [8086:1e3a] type 00 class 0x078000 pci 0000:00:1a.0: [8086:1e2d] type 00 class 0x0c0320 pci 0000:00:1b.0: [8086:1e20] type 00 class 0x040300 pci 0000:00:1c.0: [8086:1e10] type 01 class 0x060400 pci 0000:00:1c.4: [8086:1e18] type 01 class 0x060400 pci 0000:00:1d.0: [8086:1e26] type 00 class 0x0c0320 pci 0000:00:1f.0: [8086:1e4a] type 00 class 0x060100 pci 0000:00:1f.2: [8086:1e00] type 00 class 0x01018f pci 0000:00:1f.3: [8086:1e22] type 00 class 0x0c0500 pci 0000:00:1f.5: [8086:1e08] type 00 class 0x010185 pci 0000:01:00.0: [1172:1337] type 00 class 0xff0000 pci 0000:03:00.0: [10ec:8168] type 00 class 0x020000 So there is at least one configuration that doesn't work. :P Simon