Path: csiph.com!x330-a1.tempe.blueboxinc.net!usenet.pasdenom.info!gegeweb.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!feeder.erje.net!news-2.dfn.de!news.dfn.de!news.uni-stuttgart.de!news.nask.pl!news.nask.org.pl!newsfeed2.atman.pl!newsfeed.atman.pl!.POSTED!not-for-mail From: Edek Newsgroups: comp.programming.threads Subject: Re: Implicit memory barriers on x86 Date: Sat, 11 Jun 2011 22:18:22 +0200 Organization: ATMAN - ATM S.A. Lines: 72 Message-ID: References: <071a9804-ceb8-4276-bfe2-7796359170ec@16g2000yqy.googlegroups.com> <9c31e82b-efad-4737-800c-921f623384f5@l18g2000yql.googlegroups.com> NNTP-Posting-Host: 213.241.90.232 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: node2.news.atman.pl 1307823486 12885 213.241.90.232 (11 Jun 2011 20:18:06 GMT) X-Complaints-To: usenet@atman.pl NNTP-Posting-Date: Sat, 11 Jun 2011 20:18:06 +0000 (UTC) User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.17) Gecko/20110428 Linux/3.1.0-15 Thunderbird/3.1.0 In-Reply-To: Xref: x330-a1.tempe.blueboxinc.net comp.programming.threads:260 On 06/11/2011 09:30 PM, Rani Sharoni wrote: >> The Intel guide proves me *wrong* since the ordering rules are >> not as straight forward as I thought. > > Quiz: > Processor 0 Processor 1 > mov [ _y], 1 > mov [ _x], 1 mov r1, [ _y] > mov [ _y], 1 mov r2, [ _x] > > Initially x = y = 0. > Quiz: r1 = 1 and r2 = 0 is not allowed??? Is allowed. I would rather see that on p1: _y (r1) differs from p0 _y. That does not break threading stuff, on processor 1 the difference is between a) 1 -> _y release_spinlock() r1 <- _y and b) 1 -> _y r1 <- _y release_spinlock() In general, if release_spinlock would be a "black box" with possible mfence semantics, this would break stuff. (r1 could have wrong value). But AFAIK release_lock only prevents writes from moving down, not reads moving up; if you're implementing a simple lock, that is basic stuff; am I missing something? > > You can see the above inconsistency when combining the following: > 1) Stores Are Not Reordered with Other Stores - no allowing the above > 2) Intra-Processor Forwarding is Allowed - allowing the > above > > 1) Example 8-1. Stores Are Not Reordered with Other Stores > Processor 0 Processor 1 > mov [ _x], 1 mov r1, [ _y] > mov [ _y], 1 mov r2, [ _x] > Initially x = y = 0. r1 = 1 and r2 = 0 is not allowed > > 2) Example 8-5. Intra-Processor Forwarding is Allowed > Processor 0 Processor 1 > mov [ _x], 1 mov [ _y], 1 > mov r1, [ _x] mov r3, [ _y] > mov r2, [ _y] mov r4, [ _x] > Initially x = y = 0. r2 = 0 and r4 = 0 is allowed > > Rani The semantics is clever: there are two aspects of it, one is what the virtual processor does, and abother is how the actions are visible to other virtual processors and how others processor's action are visible to it. I would note that the name of the memory model includes the forwarding in its name in the manual. Edek