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From: Anthony Williams <anthony.ajw@gmail.com>
Newsgroups: comp.programming.threads
Subject: Re: questions about memory_order_seq_cst fence
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Date: Thu, 16 Jun 2011 11:19:00 +0100
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Alexander Terekhov <terekhov@web.de> writes:

> Anthony Williams wrote:
>> 
>> Edek <edek.pienkowski@gmail.com> writes:
>> 
>> > As a side note, I compiled all ops on x86_64, and atomic<int>::load
>> > is mfence/load/mfence even for relaxed. I'd need some time to analyse
>> > the thing from perspective of other ops implementations in all
>> > orderings, and this leads me to the not so subtle question:
>> 
>> Ouch. That is a seriously over-cautious implementation. Atomics should
>> not need any fences on x86_64 unless you actually write
>> atomic_thread_fence(memory_order_seq_cst)
>> 
>> See my blog entry for the required operations:
>> 
>> http://www.justsoftwaresolutions.co.uk/threading/intel-memory-ordering-and-c++-memory-model.html
>> 
>> The only one that is not a plain MOV is a seq_cst store, which is an
>> XCHG.
>
> I believe that a seq_cst load is not a plain move either...

Why do think it shouldn't be, and what do you think it should be instead?

The mapping in my blog post was confirmed by Intel processor engineers.

Anthony
-- 
Author of C++ Concurrency in Action     http://www.stdthread.co.uk/book/
just::thread C++0x thread library             http://www.stdthread.co.uk
Just Software Solutions Ltd       http://www.justsoftwaresolutions.co.uk
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