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From: Alexander Terekhov <terekhov@web.de>
Newsgroups: comp.programming.threads
Subject: Re: questions about memory_order_seq_cst fence
Date: Mon, 27 Jun 2011 14:05:07 +0200
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Masakuni Oishi wrote:
[...]
> /***************/
> // Initially
> atomic<int> x(0), y(0);
> 
> // Thread 1:
> x.store(1, memory_order_relaxed);
> 
> // Thread 2:
> r1 = x.load(memory_order_relaxed);
> y.store(1, memory_order_release);
> 
> // Thread 3:
> r2 = y.load(memory_order_acquire);
> r3 = x.load(memory_order_relaxed);
> /***************/
> 
> this code does not allow the outcome
> r1 == 1 && r2 == 1 && r3 == 0
> under the C++0x memory model.

Well,

http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html

"Example 1: Load/Load ...

Thread 0: 	

  r1 = x.load(memory_order_relaxed);
  y.store(1, memory_order_release);

Thread 1: 	
	 
  r2 = y.load(memory_order_acquire);
  r3 = x.load(memory_order_relaxed);
	 
Thread 2 (required for assertion): 	

  x.store(1, memory_order_relaxed);"
	
says that "the C++ memory model does not actually require the loads to
be ordered in this case, since thread 0's relaxed store is not
guaranteed to be seen in any particular order by thread 0's and 1's
relaxed loads. " ("thread 0's relaxed store" is meant to say "thread 2's
relaxed store" of course)

regards,
alexander.