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From: Alexander Terekhov <terekhov@web.de>
Newsgroups: comp.programming.threads
Subject: Re: questions about memory_order_seq_cst fence
Date: Tue, 21 Jun 2011 14:54:00 +0200
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Anthony Williams wrote:
[...]
> > Suppose that I can program in terms of C++MM's acquire/release. The
> > platform is x86.
> >
> > How am I supposed to ensure remote write atomicity ala IA-64 releases
> > for a particular store (relevant loads) using C++MM and NOT pessimizing
> > everything to seq_cst?
> 
> In the general case, you can't. Acquire/release is essentially pairwise
> synchronization in the C++0x MM; if you need a total order then you must
> use seq_cst.

I have no problem using seq_cst for either particular store or relevant
loads but I don't want to pessimizing everything to seq_cst.

> 
> However, in particular cases then you can order particular subsets. 

Please elaborate.

> If you have an example of code that you would like to work then I can 
> see if I can think of a way to make it work without using seq_cst 
> everywhere.
> 
> > The next question is regarding store-load fencing for particular
> > release-store and subsequent acquire-load.
> 
> One issue here is that the terminology and effects of SPARC membar
> constraints do not map cleanly onto C++0x ordering constraints. SPARC

Do you have an example for a C++MM's seq_cst fence actually not
providing a store-load barrier in compiled code on some platform?

regards,
alexander.