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From: Alexander Terekhov <terekhov@web.de>
Newsgroups: comp.programming.threads
Subject: Re: questions about memory_order_seq_cst fence
Date: Sat, 18 Jun 2011 15:42:17 +0200
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Anthony Williams wrote:
> 
> Masakuni Oishi <yamasa@bsdhouse.org> writes:
> 
> > If so, for the code 1 in my first post, is the outcome
> > r1 == 0 && r2 == 1 && r3 == 0 possible on IA-64?
> 
> I believe so.

Perhaps this is relevant:

http://download.intel.com/design/itanium/downloads/25142901.pdf

See 3.3.7.1 Total ordering of WB Releases. 

(remote write atomicity)

regards,
alexander.