Path: csiph.com!v102.xanadu-bbs.net!xanadu-bbs.net!eternal-september.org!feeder.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: =?UTF-8?B?U3TDqXBoYW5lIFp1Y2tlcm1hbg==?= Newsgroups: comp.parallel,news.announce.conferences Subject: Call for papers: Dataflow Models for Extreme Scale Computing (DFM 2014) Date: Sat, 03 May 2014 16:38:03 -0400 Organization: A noiseless patient Spider Lines: 122 Approved: Jason Riedy Message-ID: <536553AB.4090407@udel.edu> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Injection-Info: mx05.eternal-september.org; posting-host="d928f685d5403aa4cf76429412b20f16"; logging-data="28691"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18Aru2hHNRpQ7etzGnDcYAqqbyt7eIpL1k=" Cancel-Lock: sha1:nFC6RfPXvXDu5s2ZTcsdryv7s+I= Xref: csiph.com comp.parallel:1066 [Apologies if you received multiple copies of this message] FORTH WORKSHOP ON DATA-FLOW EXECUTION MODELS FOR EXTREME SCALE COMPUTING (DFM 2014) to be held in conjunction with PACT 2014 August 24, 2014, Edmonton, Alberta, Canada Important Dates: Submission Deadline: June 16th Notification of Authors: July 12th Camera Ready: July 20th The Fourth International workshop on =C3=A2=C2=80=C2=9CData-Flow Models (= DFM) for=20 extreme scale computing=C3=A2=C2=80=C2=9D will be held in conjunction wit= h PACT 2014 in=20 Edmonton, Alberta, Canada in August 2014. The purpose of DFM continues being to bring together those researchers=20 interested in novel computational models based on Data-Flow principles=20 of execution. The switch to multi-core systems has raised concurrency to=20 the level of a major issue if we are to use the increasing number of=20 cores in a chip. In the past five decades, sequential computing dominated the computer=20 architecture landscape because designers were successful at building=20 faster and faster computers by solely relying on improvements on=20 fabrication technologies and architectural/organization optimizations.=20 The most severe limitation of the sequential model, namely its inability=20 to tolerate long memory latencies has slowed down the performance gains.=20 This phenomenon is the ubiquitous Memory Wall. While various mechanisms=20 have been implemented to overcome the wall (such as extremely efficient=20 hardware prefetch support for example), they only add to another wall=20 that hampers highly efficient execution of programs and modern chip=20 design: the Power Wall. Power considerations and heat dissipation issues=20 have forced manufacturers to switch to multiple cores per chip and thus=20 move into the concurrency era. New concurrent models/paradigms are needed in order to fully utilize the=20 potential of Multi-core chips. The Data-flow model is a formal model=20 that can handle concurrency and tolerate memory and synchronization=20 latencies. Data-Flow inspired systems could also be simpler and more=20 power efficient than conventional systems. Recent work has shown that the Data-Flow principles can be used to=20 develop systems that can outperform systems based on conventional=20 techniques. Thus, it is time to revisit Data-driven computation and=20 bring it to the Multi-core and extreme scale computing. DFM 2014 solicits novel papers that include but are not limited to: - Novel Data-Flow inspired Execution models and Architectures - Functional and Single assignment based Languages. - Strict and non-strict execution models. - Compilers and tools for Data-Flow/Data-Driven systems. - Hybrid Data-driven/Control-driven systems. - Position Papers on the Future of Data-Flow in the Multi-core era and=20 beyond. DFM 2014 will accept both Full (8 pages) and Short papers (4 pages).=20 Papers should be prepared using the IEEE Proceedings format, Submit your=20 paper via the EASY CHAIR All accepted papers will appear in the IEEE Xplore Digital Library.=20 Extended versions of the best papers will be invited to submit for=20 special issue of IJPP (International Journal on Parallel Programming). STEERING Committee: Skevos Evripidou , University of Cyprus Guang Gao, University of Delaware Jean-Luc Gaudiot, Univ. of California at Irvine Vivek Sarkar, Rice University Ian Watson, University of Manchester Kei Hiraki, University of Tokyo PUBLICITY CHAIR: Giorgos Matheou, University of Cyprus St=C3=83=C2=A9phane Zuckerman, Univ. of Delaware PROGRAM COMMITTEE: Skevos Evripidou, University of Cyprus Guang Gao, University of Delaware Jean-Luc Gaudiot, Univ. of California at Irvine Vivek Sarkar, Rice University Ian Watson, University of Manchester Kei Hiraki, University of Tokyo David Abramson, Monash University Costas Kyriacou, Frederic University Pedro Trancoso, University of Cyprus Kyriacos Stavrou, Intel Labs Barcelona, SP John Feo, Pacific Northwest National Laboratory Bob Iannucci, CMU, Silicon Valley, USA Wallid Najjar, University of California, Riverside Wolfgang Karl, KIT, Germany Mark Oskin, University of Washington Andrew Sohn, NJIT, USA Reiner Hartenstein, TU Kaiserslautern Kemal Ebcio=C3=84=C2=9Flu, Global Supercomputing Corp. Kevin Hammond, University of St Andrews Roberto Giorgi, University of Sienna Robert Clay, Sandia National Labs Sven-Bodo Scholz, Heriot-Watt University St=C3=83=C2=A9phane Zuckerman, Univ. of Delaware PROCEEDING CHAIR: Costas Kyriacou, Frederic University Cyprus --=20 St=C3=83=C2=A9phane Zuckerman Computer Architecture & Parallel Systems Laboratories (CAPSL) University of Delaware, 201G Evans Hall, Newark DE 19716 Work#: 302 831 6534 / Cell#: +1 302 883 9979