Path: csiph.com!usenet.pasdenom.info!aioe.org!.POSTED!not-for-mail From: "Rod Pemberton" Newsgroups: alt.os.development,comp.os.msdos.programmer,alt.lang.asm Subject: Re: detecting emulation or console windows Date: Mon, 02 Jun 2014 19:25:30 -0400 Organization: Aioe.org NNTP Server Lines: 82 Message-ID: References: NNTP-Posting-Host: CNsg4fVcCsvs3UaOgZtQCw.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed; delsp=yes Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Opera Mail/12.16 (Linux) X-Notice: Filtered by postfilter v. 0.8.2 Xref: csiph.com comp.os.msdos.programmer:1388 On Mon, 02 Jun 2014 12:05:34 -0400, James Harris wrote: > "Rod Pemberton" wrote in message > news:op.xgtw0lnh6zenlw@localhost... >> I have a whole bunch of DOS .com's which >> enable and disable A20. In DOS, you have to >> boot clean, i.e., no XMS memory manager to >> correctly detect and use A20. XMS memory managers >> emulate A20. > > You mean they enable it and then program segment tables > to mimic wrapping as needed? I'm not sure what XMS does with A20. It's emulated somehow. I'd have to recheck, but I think XMS wouldn't let you enable or disable A20 via the standard methods. > As this has come up I have to say that I was surprised at > the start of this thread when you mentioned that your new > project started from DOS the way that your OS does.I remember discussing > how complex that made your OS startup. > Did you not want to do away with that in your new project? This doesn't use anything from my OS. It uses standard DJGPP (GCC) C compiler and DPMI functionality. It doesn't need to dump out the DPMI host, or DOS, or need a special TSR to start, etc like my OS. I'm hoping to keep it to only DJGPP and DPMI functionality, excluding some potential direct hardware access. For it to be useful, it needs to be made to operate somewhat faster. >> AIUI, the Int instruction should force memory coherency >> and/or cache flush etc to ensure that the memory wrap or >> unwrap is in effect prior to generating the interrupt. > > Is that needed? It's done. It's been done. It works. Codewise, it looks clean-er... > We discussed this on alt.os.development a few years ago > and, Yes. > IIRC, came to the conclusion that the A20 mask > occurs between the CPU and its caches even if those > caches are on chip. (There is an A20 gate input pin > on CPUs with caches.) So the test of A20 is one of > addressing, not memory values. In other words there > is no need for memory coherency such as to allow > updated values to drain to memory before reading > them back from the other address. I don't remember the conclusion, but as long as the cache is up to date in terms of A20 state at the time of the memory writes to the vector and high address, it won't matter if the value is in cache or memory. And, you know about both techniques, so if you want to search for one where the Int method doesn't work, it's your choice. I only had a half dozen machines to test on. > The only potential problem I can remember would be > a machine such as an old pre-486 (i.e. one which has > no on-chip cache) then an external cache and then > the A20 gate. That was theoretcical. We didn't > identify any particular machine which was built > that way. That would be a "strange bird", at least for x86. IIRC, the 68000 series had an external MMU for the first few processors, but I recall if they had an external cache. Rod Pemberton P.S. Opera has an option which says it's supposed to be wrapping lines for Usenet so I'm sending this extra long one to see what happens ...