Path: csiph.com!fu-berlin.de!uni-berlin.de!not-for-mail From: pyvhdl@gmail.com Newsgroups: comp.lang.python.announce Subject: ANN: 'PyVHDL' A VHDL simulator written in Python with a full featured Eclipse GUI Date: Tue, 1 Nov 2016 12:57:53 -0700 (PDT) Lines: 29 Approved: python-announce-list@python.org Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Trace: news.uni-berlin.de ZJjzDPu+2UEn97bDiWFzYwtDx9XgktNkSEULDpHvivtQ== X-Orig-Path: e187no553740itc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Return-Path: X-Original-To: python-announce@python.org Delivered-To: python-announce-list@mail.python.org X-Spam-Status: OK 0.020 X-Spam-Evidence: '*H*': 0.96; '*S*': 0.00; 'subject:Python': 0.05; 'classes.': 0.07; "subject:' ": 0.07; 'subject:ANN': 0.07; 'python': 0.09; 'concurrent': 0.09; 'ide': 0.09; 'logic': 0.09; 'subject: \n ': 0.15; 'license:': 0.16; 'mips': 0.16; 'simulate': 0.16; 'subject:GUI': 0.16; 'alpha': 0.18; 'tests': 0.18; 'bit': 0.23; 'language': 0.23; 'said,': 0.23; 'url:io': 0.23; 'header :User-Agent:1': 0.26; 'written': 0.27; 'implemented': 0.27; 'cpu': 0.29; 'fork': 0.29; 'announce': 0.29; 'instruction': 0.29; 'included': 0.32; 'implement': 0.32; 'received:google.com': 0.32; 'running': 0.33; 'gnu': 0.33; 'version:': 0.33; 'url:en': 0.33; 'run': 0.34; 'displays': 0.35; 'release': 0.35; 'received:209.85': 0.36; 'skip:- 10': 0.36; 'version': 0.37; 'received:209': 0.38; 'received:209.85.214': 0.39; 'standard': 0.40; 'subject:with': 0.40; 'received:io': 0.40; 'received:psf.io': 0.40; 'from:no real name:2**0': 0.61; 'e-mail:': 0.61; 'email addr:gmail.com': 0.62; 'here:': 0.62; 'license': 0.65; 'to:addr:comp-lang-python- announce': 0.68; 'design.': 0.71; 'to:addr:moderators.isc.org': 0.77; 'complexity': 0.84; 'simulation.': 0.84; 'more?': 0.91; 'plasma': 0.91; 'message-id:@googlegroups.com': 0.93 Delivered-To: comp-lang-python-announce@moderators.isc.org X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:path:newsgroups:date:complaints-to :injection-info:nntp-posting-host:user-agent:mime-version:message-id :subject:from:injection-date:to:content-transfer-encoding; bh=9A8m1UxRlOwnBuyZEfDgUM2cG8k7e1nwEYhPUvZEGnU=; b=j0egs0ydyEYk9PlhHWo+qk5jmzpnQirUa1IhS7PqXGIiKSkTZamqqn04ZZmbM0a4if GYC3ekWW5HSb9rCeiKx9k+FoqXmGMse65Kdhbe2XzuxHGyZC1QX+xb8XPbs4lx9Jc0J+ hjZjeN7/JEl8RoCAFMv3/DJlm8M508wcvp6HwFBQP9E7qgUQdCBRwFZzWU83IK+MPBH7 TMaExXxvKa4U6dl6OboeNY2CZpQ6IYiTZrv7ftOTlQ7YUPkcMfo3OiPHMINkM/JwpG2o YqFJio13NCi/wSP42FQN6PeGTxHcKtCcUh4WFRuYXUhUJdW+nn9WvHOzi7cEgkyH6F/Q JOAg== X-Gm-Message-State: ABUngvejDFv3DkKArD/33rfllGObjlFGTTiOg+yibcE2Cm8aN1QE65DiSVyLR8eukdynfoJk3ZP1R5XCmOb9fnME5mk+zdc= X-Received: by 10.107.145.4 with SMTP id t4mr159100iod.38.1478030275780; Tue, 01 Nov 2016 12:57:55 -0700 (PDT) X-Received: by 10.157.4.119 with SMTP id 110mr1788113otc.11.1478030275741; Tue, 01 Nov 2016 12:57:55 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:c4ef:8760:30b2:ec3a:36e:5263; posting-account=Axrn7goAAAA5qSrxa9s5PWNZ-LbhCWE9 User-Agent: G2/1.0 Injection-Date: Tue, 01 Nov 2016 19:57:55 +0000 X-Mailman-Approved-At: Wed, 02 Nov 2016 08:02:45 -0400 X-BeenThere: python-announce-list@python.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Announcement-only list for the Python programming language List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Mailman-Original-Message-ID: Xref: csiph.com comp.lang.python.announce:2298 I am pleased to announce the first alpha release of PyVHDL.=20 What is PyVHDL? --------------- It is a VHDL simulator which translates VHDL processes to python bytecode. = Standard Logic, and Standard Logic Vector types are implemented as python c= lasses. Concurrent processes can be written in Python to create testbenches= , or implement any complexity of logic design. These Python processes are s= eamlessly included in the simulations. PyVHDL includes a fork of the ZamiaCAD VHDL IDE for editing designs, and ru= nning simulations. ZamiaCAD also displays signal waveforms generated during= the simulation. PyVHDL is able to simulate the Plasma 32 bit MIPS CPU design. All instructi= on tests run successfully, That said, not all VHDL language features are im= plemented at this time, hence the alpha designation. How can I learn more? -------------------- To try out PyVHDL, start at the documentation here: http://pyvhdl-docs.readthedocs.io/en/latest/ ----------------------- version: 0.0.1 ALPHA license: GNU General Public License Version 3 e-mail: pyvhdl@gmail.com