Path: csiph.com!usenet.pasdenom.info!aioe.org!eternal-september.org!feeder.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: =?UTF-8?Q?Joshua_Cranmer_=f0=9f=90=a7?= Newsgroups: comp.lang.java.programmer Subject: Re: just for fun: JSL: "q*100" hand-optimized to "(q<<6)+(q<<5)+(q<<2)" Date: Wed, 26 Nov 2014 08:10:18 -0600 Organization: A noiseless patient Spider Lines: 30 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 26 Nov 2014 14:10:06 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="8cedddb29338592f734c41b16a68fadc"; logging-data="19397"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/ZhaYuY/lt+Tcp6/CIEvL8qjQKOcEZLRs=" User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:34.0) Gecko/20100101 Thunderbird/34.0 In-Reply-To: Cancel-Lock: sha1:SIOG+uKq2Q+gW7NPr7RvJ5KvjJU= Xref: csiph.com comp.lang.java.programmer:30418 On 11/26/2014 2:53 AM, Andreas Leitgeb wrote: > Last book I had mentioning those was about 8088/86 processors :-) > And latest hearsay was, that on sufficiently new cpus even a floating > point operations took one mere cpu-cycle - not so sure about that anymore. Eh..... modern processors are heavily pipelined, so "taking one cpu-cycle" is a bit of a misnomer. The latencies of an SSE floating point add is 3, but it has a throughput of 1 per cycle. Although I should point out that x86 processors have something like 10-15 stages of "fetch" and "decode" due to the complex nature of their instruction set... which means the most painful thing you can do is mispredict a branch and have to flush the pipeline. > I'm not very knowing about modern cpu feature names, but not-requiring > a "superlane" sure sounds like an advantage in the lowest levels. A modern desktop x86 processor is an out-of-order, superscalar processor. Effectively, this means that the "execute instruction" stage is basically a step where the processor ignores the order of instructions you listed in the assembly but rather throws them in several execution units as they become available. The Haswell microarchitecture (the latest as of this writing) has 8 execution units or ports: Two for loads, two for stores, one for branches, one for vectors, two for floating point or vectors. Basic integer operations can operate in any of the last four ports. -- Beware of bugs in the above code; I have only proved it correct, not tried it. -- Donald E. Knuth