Path: csiph.com!usenet.pasdenom.info!aioe.org!.POSTED!not-for-mail From: "Rod Pemberton" Newsgroups: comp.lang.forth Subject: Re: @ and optimization Date: Sat, 26 Apr 2014 08:50:32 -0400 Organization: Aioe.org NNTP Server Lines: 42 Message-ID: References: <27ilk9dvau3o08tmi9ccedohs8j8oujac2@4ax.com> <2014Apr23.150747@mips.complang.tuwien.ac.at> <2014Apr24.191024@mips.complang.tuwien.ac.at> <2014Apr25.104047@mips.complang.tuwien.ac.at> <2014Apr25.172651@mips.complang.tuwien.ac.at> <2014Apr25.192230@mips.complang.tuwien.ac.at> NNTP-Posting-Host: CNsg4fVcCsvs3UaOgZtQCw.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed; delsp=yes Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Opera Mail/12.16 (Linux) X-Notice: Filtered by postfilter v. 0.8.2 Xref: csiph.com comp.lang.forth:29861 On Fri, 25 Apr 2014 13:22:30 -0400, Anton Ertl wrote: > Andrew Haley writes: >> and b) even if they don't the hardware may >> replace two fetches from the same address with a single one. And this >> is not "weird" hardware, but almost every modern (32 bits and up) >> design. Even the venerable x86 needs a StoreLoad barrier if you want >> sequential consistency. > > Memory ordering/sequential consistency has nothing to do with this, as > established above. And sure, if you have two loads from the same > addresses in cached memory, the second one will be served from the > cache. But devices that have a side effect on reading are not in > cached memory, and two loads will result in two accesses (and two > times the side effect). Coherency means what is in the cache matches what is in memory. With two reads to the same address, if memory hasn't changed any, then both "foo @" will be from the cache and have the same value. With two reads to the same address, if memory has changed between reads, e.g., perhaps via memory mapped hardware, then the first and second "foo @" will have the different values. The first will be loaded from the cache. The second may be loaded from the memory or loaded from an invalidated and re-loaded cache, depending on the design of the coherency logic. If what's in the cache doesn't match memory for the second read, then the microprocessor's coherency logic is *broken*. Excluding the improved memory speed of caching, the caching operation should function as if there was no cache present, i.e., as if the read or write was directly to memory without buffering, without memory read optimization, etc. If the memory changes between reads, the processor can update the cache at various points in time depending on the design. E.g., at the hardware write to memory, at the next read, etc. Rod Pemberton