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From: "Rod Pemberton" <dont_use_email@xnothavet.cqm>
Newsgroups: comp.lang.forth
Subject: Re: @ and optimization
Date: Sat, 26 Apr 2014 20:33:58 -0400
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On Sat, 26 Apr 2014 17:52:43 -0400, Alex McDonald <blog@rivadpm.com> wrote:
> on 26/04/2014 13:50:35, "Rod Pemberton" wrote:
>> On Fri, 25 Apr 2014 13:22:30 -0400, Anton Ertl
>> <anton@mips.complang.tuwien.ac.at> wrote:
>>> Andrew Haley <andrew29@littlepinkcloud.invalid> writes:

>>>> and b) even if they don't the hardware may
>>>> replace two fetches from the same address with a single one.  And this
>>>> is not "weird" hardware, but almost every modern (32 bits and up)
>>>> design.  Even the venerable x86 needs a StoreLoad barrier if you want
>>>> sequential consistency.
>>>
>>> Memory ordering/sequential consistency has nothing to do with this, as
>>> established above.  And sure, if you have two loads from the same
>>> addresses in cached memory, the second one will be served from the
>>> cache.  But devices that have a side effect on reading are not in
>>> cached memory, and two loads will result in two accesses (and two
>>> times the side effect).
>>
>> Coherency means what is in the cache matches what is in memory.
>
> Coherency says nothing about what value is in memory. Coherency ensures
> that the value of an item retrieved from non-disjoint locations by a
> coupled processor is the most up-to-date value.
>

http://en.wikipedia.org/wiki/Cache_coherency


RP