Path: csiph.com!eternal-september.org!feeder.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.forth Subject: Re: embedded forth Date: Sat, 4 Feb 2017 04:22:33 -0500 Organization: A noiseless patient Spider Lines: 78 Message-ID: References: <49b3566a-3842-4f9f-a47f-a66590625fef@googlegroups.com> <2017Jan23.100126@mips.complang.tuwien.ac.at> <423bc49f-f47d-415d-80d6-53fb0472c929@googlegroups.com> <7f7415ad-9ba0-4d9a-ba9d-d08fad5c344e@googlegroups.com> <92d07db1-18b7-410e-a77c-d7ab4f6606d8@googlegroups.com> <4b343d40-7252-4919-8e0d-aeace01a87cd@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 4 Feb 2017 09:20:48 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="34c5b97265726e4c8d7df6f3b61d23bc"; logging-data="22899"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/LWhqHlgi9+fP/a7zm24FM" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.7.0 In-Reply-To: <4b343d40-7252-4919-8e0d-aeace01a87cd@googlegroups.com> Cancel-Lock: sha1:yXk+Tu975WELSAnG2eD+jgOpLZE= Xref: csiph.com comp.lang.forth:54623 On 1/29/2017 1:20 PM, Ilya Tarasov wrote: >>> Please specify. Do you mean approach, based on sin(a+b)? If so, >>> we use sin(a+b) = sin(a)*cos(b) + cos(a)*sin(b), and this >>> require multiplication of sin and cos values. Is it what you >>> talking about? >> >> I am talking about the fact that you are making a big distinction >> between a CORDIC computation and a multiplier when there is only >> one real difference. A CORDIC computation will use virtually the >> same resources in the FPGA fabric as an equivalent multiply, likely >> more. But the difference is that most FPGAs include hard IP >> multipliers! Hard IP uses *much* less silicon area than anything >> done in the fabric. Altera has recently announced hard IP floating >> point ALUs. > > You still don't list your algorithm details. Maybe it will consume > LUTs in other parts, for control structures or so on. Of course, I > know about hard multipliers (with 10+ years experience of approved > Xilinx trainer it is very hard to miss something important). You need > to store angles, sin/cos values and provide datapath control > (sequental, pipelined or mixed). If you still can provide maximum > error with 1 LSB for any datawidth, it is interesting. If not, it is > an approximation, suitable for some purposes. You mean I don't have a fully coded VHDL example at 32 bits word width to show you? No, I don't. But that is not needed. The control logic would be trivial compared to thousands of LUTs. The only extra logic required is on the order of a handful of adders and/or multiplexers. I took the time to do some calculations which show to get results accurate to all but the last bit of a 32 bit word would require a sin() table with a quarter of a million values. That would put it outside the realm of most FPGAs and require external memory. However if external memory is used, this is not only feasible but simple. The only issue is to get the step sizes small enough so the two approximations do apply, sin(b)=b and cos(b)=1.0 to within the required accuracy. I've never seen an application that needed 32 bits of sin/cos. The DDS work I've done was related to real world signals which are limited to some 20 to 24 bits of SNR when converting between analog and digital at very best. I was pretty happy when I showed myself I could get 20 bits without any real trouble. >> At this point I have lost my interest in debating this much >> further. CORDIC is not the only method of calculating rotating >> vectors. It is useful where you have a lack of computing >> resources. If multiplication is readily available other methods >> compare very favorably. > > So what is your method? > >>> because of reconfiguration capabilities. With Forth CPU we can >>> additionally adapt this system to the man who works with hardware >>> and tightly connect CPU to hardware. >> >> What exactly is a "Forth CPU"? > > I have several designs. Now it is 7th generation of > microarchitecture, with hardware multithreading, targeting Spartan-6 > and 7-series Xilinx FPGAs. But that doesn't tell me what a Forth CPU is. I assume you really mean a stack machine. When you say "hardware multithreading", I expect this is using the pipeline to facilitate multiple threads rather than concurrent instructions in a single thread? >> How fast can a CORDIC be done? > > From 175 MHz to 300-400, depends on FPGA famuly, function calculated, > datawidth and serial/parallel architecture. Yeah, that would be a typical pipelined speed. -- Rick C