Path: csiph.com!usenet.pasdenom.info!weretis.net!feeder1.news.weretis.net!news1.tnib.de!feed.news.tnib.de!news.tnib.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: vandys@vsta.org Newsgroups: comp.lang.forth Subject: Re: RTX2000 optimization Date: 23 Oct 2012 17:54:46 GMT Lines: 20 Message-ID: References: <3b14c2ce-6e19-4df7-abc2-cf169dcf9665@googlegroups.com> <07562d07-693e-48ec-b996-610c4eba1cc9@k21g2000vbj.googlegroups.com> <02194379-ee88-4ea5-a65c-ca78c88545e0@tr7g2000pbc.googlegroups.com> <0LednT1JJZiAzhvNnZ2dnUVZ8iOdnZ2d@supernews.com> X-Trace: individual.net +E7SJ/gmUjMVLqUGx1QX7gjoQ2XLu1Ip7sECQUE6MoExsvEAKFhMNzqiUvBJx2KViq X-Orig-Path: not-for-mail Cancel-Lock: sha1:Wpi9M/UXXsQ8M6awuYNRBq3w2+c= User-Agent: tin/1.8.3-20070201 ("Scotasay") (UNIX) (Linux/3.2.0-32-generic-pae (i686)) Xref: csiph.com comp.lang.forth:16623 Andrew Haley wrote: > Hugh Aguilar wrote: >>> Years ago, there was a processor that used a few bits, like two, for >>> conditional execution of each instruction. >> Isn't that the way that the ARM works? > It was, but it's mostly been dropped in ARM 64 because "Benchmarking > shows that modern branch predictors work well enough that predicated > execution of instructions does not offer sufficient benefit to justify > its significant use of opcode space, and its implementation cost in > advanced implementations." FWIW, the Propeller CPU has conditional execution too. I did a fair amount of hand-coding of assembly for it, and came away not liking its instruction set very much at all. MIPS is my all-time favorite, but I'd even take 32-bit x86 over Propeller. -- Andy Valencia Home page: http://www.vsta.org/andy/ To contact me: http://www.vsta.org/contact/andy.html